Metal capped copper interconnect
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0376199
(2006-03-16)
|
등록번호 |
US-7495338
(2009-02-24)
|
발명자
/ 주소 |
- Lane,Michael
- Chiras,Stefanie R.
- Spooner,Terry A.
- Rosenberg,Robert
- Edelstein,Daniel C.
|
출원인 / 주소 |
- International Business Machines Corporation
|
대리인 / 주소 |
Connolly Bove Lodge & Hutz LLP
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
10 |
초록
▼
A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the o
A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.
대표청구항
▼
We claim: 1. A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from the group consisting of iridium, osmium and rhenium; and an interfacial region, wherein the interfacial region comprises
We claim: 1. A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from the group consisting of iridium, osmium and rhenium; and an interfacial region, wherein the interfacial region comprises at least 80 atomic percent of the one or more metals. 2. The conducting material of claim 1, wherein the interfacial region comprises at least 90 atomic percent of iridium. 3. The conducting material of claim 2, wherein the conducting core region comprises from 0.001 atomic percent to 0.4 atomic percent of iridium. 4. The conducting material of claim 2, wherein the conducting core region comprises from 0.001 atomic percent to 0.2 atomic percent of iridium. 5. The conducting material of claim 2, further comprising a seed region, wherein the seed region comprises from 0.5 atomic percent to 4 atomic percent of iridium. 6. The conducting material of claim 1, wherein the interfacial region is from 5 Å to 20 Å in thickness. 7. The conducting material of claim 2, wherein the electrical resistivity of the conducting material is 2.3 μΩ/cm or less. 8. The conducting material of claim 1, wherein the conducting core region comprises from 0.001 atomic percent to 0.4 atomic percent of the one or more metals. 9. A semiconductor structure comprising: a trench or a via disposed within a dielectric material, wherein the trench or via includes an underlayer disposed along the sidewalls of the trench or the via; a copper conductor core within the trench or the via, wherein the conductor core comprises from 0.01 atomic percent to 0.6 atomic percent of one or more metals selected from the group consisting of iridium, osmium and rhenium; and an interfacial layer comprising 80 atomic percent or greater of the one or more metals. 10. The semiconductor structure of claim 9, wherein the interfacial region comprises 90 atomic percent of iridium or greater. 11. The semiconductor structure of claim 10, wherein the copper conductor core comprises from 0.001 atomic percent to 0.4 atomic percent of iridium. 12. The semiconductor structure of claim 10, wherein the copper conductor core comprises from 0.001 atomic percent to 0.2 atomic percent of iridium. 13. The semiconductor structure of claim 10, further comprising a seed region disposed on the underlayer, wherein the seed region comprises from 0.5 atomic percent to 4 atomic percent of iridium. 14. The semiconductor structure of claim 9, wherein the interfacial region is about 5 Å to about 20 Å in thickness. 15. The semiconductor structure of claim 10, wherein the electrical resistivity of the conducting material is 2.3 μΩ/cm or less. 16. The semiconductor structure of claim 9, wherein the conducting core region comprises from 0.00 1 atomic percent to 0.4 atomic percent of the one or more metals. 17. A conducting material comprising: a seed region comprising copper and 0.3 atomic percent to 1.8 atomic percent of iridium; a conducting core region comprising copper and from 0.04 atomic percent to 0.1 atomic percent of iridium; and an interfacial region, wherein the interfacial region comprises at least 98 atomic percent iridium. 18. The conducting material of claim 17, wherein the conducting core region comprises from 0.05 atomic percent to 0.08 atomic percent of iridium. 19. The conducting material of claim 17, wherein the interfacial region is from 5 Å to 20 Å in thickness. 20. The conducting material of claim 17, wherein the electrical resistivity of the conducting material is 2.1 μΩ/cm or less.
이 특허에 인용된 특허 (10)
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Daniel Charles Edelstein ; James McKell Edwin Harper ; Chao-Kun Hu ; Andrew H. Simon ; Cyprian Emeka Uzoh, Copper interconnection structure incorporating a metal seed layer.
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Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
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Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Integrated circuit inductor structure formed employing copper containing conductor winding layer clad with nickel contai.
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Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
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Paranjpe, Ajit P.; Moslehi, Mehrdad M.; Bubber, Randhir S.; Velo, Lino A., Method for fabricating a semiconductor chip interconnect.
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Ajit P. Paranjpe ; Mehrdad M. Moslehi ; Lino A. Velo ; Thomas R. Omstead ; David R. Campbell, Sr. ; Zeming Liu ; Guihua Shang, Method for forming a copper film on a substrate.
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Nogami Takeshi ; Dubin Valery ; Cheung Robin, Method of electroplating a copper or copper alloy interconnect.
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Kawai Michifumi,JPX ; Satoh Ryohei,JPX ; Yamada Osamu,JPX ; Matsuda Eiji,JPX ; Ishino Masakazu,JPX ; Inoue Takashi,JPX ; Sotokawa Hideo,JPX ; Kyoui Masayuki,JPX, Multilayer substrates methods for manufacturing multilayer substrates and electronic devices.
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Ting Chiu ; Dubin Valery, Plated copper interconnect structure.
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Zhang Jiming ; Denning Dean J., Process for forming a semiconductor device.
이 특허를 인용한 특허 (1)
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Yang, Chih-Chao; Spooner, Terry A.; van der Straten, Oscar, Interconnect structure containing non-damaged dielectric and a via gouging feature.
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