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Concurrent optimization of physical design and operational cycle assignment

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0081823 (2005-03-15)
등록번호 US-7496879 (2009-02-24)
발명자 / 주소
  • Rohe,Andre
  • Teig,Steven
출원인 / 주소
  • Tabula, Inc.
대리인 / 주소
    Adeli & Tollen LLP
인용정보 피인용 횟수 : 31  인용 특허 : 87

초록

Some embodiments provide a method of designing a configurable integrated circuit ("IC") with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations co

대표청구항

We claim: 1. A method of designing an integrated circuit ("IC") comprising a plurality of configurable circuits including a plurality of configurable interconnect circuits, the method comprising: concurrently assigning each of a plurality of operations in an IC design to an operational cycle and a

이 특허에 인용된 특허 (87)

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이 특허를 인용한 특허 (31)

  1. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  2. Teig, Steven; Schmit, Herman; Huang, Randy Renfu, Configurable IC having a routing fabric with storage elements.
  3. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
  4. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
  5. Voogel, Martin; Teig, Steven; Chandler, Trevis, Configurable storage elements.
  6. Chandler, Trevis; Redgrave, Jason; Voogel, Martin, Configuration context switcher.
  7. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  8. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  9. Redgrave, Jason; Voogel, Martin; Teig, Steven, Controllable storage elements for an IC.
  10. Caldwell, Andrew; Teig, Steven, Decision modules.
  11. Mihal, Andrew C.; Teig, Steven, Detailed placement with search and repair.
  12. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor.
  13. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore.
  14. Miller, Marc; Teig, Steven; Hutchings, Brad, Integrated circuit (IC) with primary and secondary networks and device containing such an IC.
  15. Hsu, Chin-Hsiung; Yang, Chun-Chih, Methods for reducing congestion region in layout area of IC.
  16. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  17. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  18. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  19. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
  20. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
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  27. Teig, Steven; Caldwell, Andrew, Timing operations in an IC with configurable circuits.
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  31. Redgrave, Jason, Users registers implemented with routing circuits in a configurable IC.
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