초록 ▼

Fractal memory systems and methods include a fractal tree that includes one or more fractal trunks. One or more object circuits are associated with the fractal tree. The object circuit(s) is configured from a plurality of nanotechnology-based components to provide a scalable distributed computing ar

Fractal memory systems and methods include a fractal tree that includes one or more fractal trunks. One or more object circuits are associated with the fractal tree. The object circuit(s) is configured from a plurality of nanotechnology-based components to provide a scalable distributed computing architecture for fractal computing. Additionally, a plurality of router circuits is associated with the fractal tree, wherein one or more fractal addresses output from a recognition circuit can be provided at a fractal trunk by the router circuits.

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The embodiments of an invention in which an exclusive property or right is claimed are defined as follows: 1. A fractal memory system, comprising: a fractal tree comprising at least one fractal trunk; at least one recognition trigger electrode that routes signals in said fractal tree; and at least

The embodiments of an invention in which an exclusive property or right is claimed are defined as follows: 1. A fractal memory system, comprising: a fractal tree comprising at least one fractal trunk; at least one recognition trigger electrode that routes signals in said fractal tree; and at least one object circuit associated with said fractal tree, wherein said object circuit is configured from a plurality of nanotechnology-based components to provide a scalable distributed computing architecture. 2. The system of claim 1 further comprising a plurality of router circuits associated with said fractal tree, wherein at least one fractal address output from said at least one object circuit is provided at said at least one fractal trunk by said plurality of router circuits. 3. The system of claim 1 wherein data is transmittable to at least one fractal address of said at least object circuit by specifying said at least one fractal address at said at least one fractal trunk. 4. The system of claim 1 wherein data is transmittable from said at least one object circuit to at least one other object circuit associated with said fractal tree by extracting an output and address from at least one output of at least one fractal trunk of said fractal tree and utilizing said output and address as an input and address to said fractal trunk. 5. The system of claim 1 wherein said object circuit comprises at least one logic circuit. 6. The system of claim 1 wherein said object circuit comprises a microprocessor. 7. The system of claim 1 wherein said at least one object circuit comprises at least one ensemble electrode, wherein said object circuit provides a positive feedback function to said at least one ensemble electrode. 8. The system of claim 1 wherein said at least one object circuit comprises a plurality neural nodes configured as an ensemble of ensembles. 9. The system of claim 1 wherein temporal data is utilized to encode recognition accuracy for said at least one object circuit. 10. The system of claim 1 wherein said plurality of nanotechnology-based components comprise an artificial synapse. 11. The system of claim 1 wherein said plurality of nanotechnology-based components comprise a physical neural network. 12. A fractal memory system, comprising: a fractal tree comprising at least one fractal trunk; at least one object circuit associated with said fractal tree, wherein said object circuit is configured from a plurality of nanotechnology-based components to provide a scalable distributed computing architecture; and a plurality of router circuits associated with said fractal tree, wherein at least one fractal address output from said at least one object circuit is provided at said at least one fractal trunk by said plurality of router circuits, and said at least one object circuit and said fractal tree are configured as a fractal memory chip, wherein a plurality of said fractal memories are stacked in association with a plurality of router chips to provide an enhanced fractal tree structure. 13. A fractal memory method, comprising: providing a fractal tree comprising at least one fractal trunk; associating at least one object circuit with said fractal tree, wherein said object circuit is configured from a plurality of nanotechnology-based components to provide a scalable distributed computing architecture and wherein said layout of said object circuits is based on a circuit layout in which a distance from each object circuit through an output electrodes to an output point comprises a same distance. 14. The method of claim 13 further comprising associating a plurality of router circuits with said fractal tree, wherein at least one fractal address output from said at least one object circuit is provided at said at least one fractal trunk by said plurality of router circuits. 15. The method of claim 13 further comprising transmitting data to at least one fractal address of said at least object circuit by specifying said at least one fractal address at said at least one fractal trunk. 16. The method of claim 13 further comprising transmitting data from said at least one object circuit to at least one other object circuit associated with said fractal tree by extracting an output and address from at least one output of at least one fractal trunk of said fractal tree and utilizing said output and address as an input and address to said fractal trunk. 17. The method of claim 13 wherein said object circuit comprises at least one logic circuit. 18. The method of claim 13 wherein said object circuit comprises a microprocessor. 19. The method of claim 13 wherein said at least one object circuit comprises at least one ensemble electrode, wherein said object circuit provides a positive feedback function to said at least one ensemble electrode. 20. The method of claim 13 wherein said at least one object circuit comprises a plurality neural nodes configured as an ensemble of ensemble electrodes. 21. The method of claim 13 further comprising utilizing temporal data to encode recognition accuracy for said at least one object circuit. 22. The method of claim 13 further comprising configuring said at least one object circuit and said fractal tree as a fractal memory chip, wherein a plurality of said fractal memories are stacked in association with a plurality of router chips to provide an enhanced fractal tree structure. 23. The method of claim 13 wherein said plurality of nanotechnology-based components comprise an artificial synapse.