Electronic apparatus having a core conductive structure within an insulating layer
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/535
H01L-023/52
출원번호
US-0215367
(2005-08-29)
등록번호
US-7504674
(2009-03-17)
발명자
/ 주소
Farrar,Paul A.
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Schwegman, Lundberg & Woessner, P.A.
인용정보
피인용 횟수 :
9인용 특허 :
233
초록▼
Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H2 plasma treatment, and
Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H2 plasma treatment, and depositing a capping adhesion/barrier layer on the core conductive layer after the H2 plasma treatment. The multilayer dielectric structure provides an insulating layer for around the core conducting layer. The H2 plasma treatment removes unwanted oxide from the surface region of the core conducting layer such that the interface between the core conducting layer and the capping adhesion/barrier is substantially free of oxides.
대표청구항▼
What is claimed is: 1. An electronic device comprising: an insulating layer; and a conductive structure within the insulating layer, the conductive structure including: a first conducting layer structured as two conductive layers; a core conductor disposed on and within the first conducting layer;
What is claimed is: 1. An electronic device comprising: an insulating layer; and a conductive structure within the insulating layer, the conductive structure including: a first conducting layer structured as two conductive layers; a core conductor disposed on and within the first conducting layer; and a capping layer disposed on and covering the core conductor and the first conducting layer, the capping layer being a conductor, the capping layer in contact with at least a center portion of the core conductor and a top portion of the two conductive layers of the first conducting layer such that contact with the first conducting layer is limited to the top portion and inner surfaces of the first conducting layer, the inner surfaces containing the core conductor, the capping layer having at least one property from a group of an adhesion property and a barrier property, wherein an interface between the capping layer and the core conductor is substantially free of an oxide. 2. The electronic device of claim 1, wherein a top surface of the core conductor is substantially at a level with a top surface of the insulating layer. 3. The electronic device of claim 1, wherein the two conductive layers are structured as a first layer and a seed layer, the first layer having at least one property from the group of an adhesion property and a barrier property. 4. The electronic device of claim 3, wherein the first layer includes a refractory metal, a compound of nitrogen and a tantalum alloy, or a compound of nitrogen and a tungsten alloy. 5. The electronic device of claim 1, wherein the core conductor includes copper, silver, a copper alloy, or a silver alloy. 6. The electronic device of claim 1, wherein the capping layer includes titanium, zirconium, hafnium, or nitrides of titanium, zirconium, or hafnium. 7. The electronic device of claim 1, wherein the capping layer has a thickness ranging from about 5 Å to about 40 Å. 8. The electronic device of claim 1, wherein the insulating layer includes a polymer layer, a foamed polymer layer, or a fluorinated polymer layer. 9. The electronic device of claim 1, wherein the insulating layer includes a polyimide layer, a foamed polyimide layer, or a fluorinated polyimide layer. 10. The electronic device of claim 1, wherein the insulating layer includes an oxide layer, a fluorinated oxide layer, a silicon dioxide layer, or an aerogel layer. 11. The electronic device of claim 1, wherein the insulating layer is disposed on a dielectric structure having a via to connect to lower level metallizations or devices in a substrate. 12. The electronic device of claim 1, wherein a portion of the insulating layer includes an opening between the core conductor and another conductor to provide an air bridge structure. 13. The electronic device of claim 1, wherein the conductive structure includes a wiring structure in an integrated circuit. 14. The electronic device of claim 1, wherein the conductive structure includes a wiring structure in a memory device. 15. The electronic device of claim 1, wherein the conductive structure includes a wiring structure in a controller coupled to an integrated circuit in an electronic system. 16. The electronic device of claim 1, wherein the core conductive structure essentially consists of aluminum, silver, gold, or combinations thereof, the core conductive structure having a hydrogen-plasma treated surface to provide the interface between the capping layer and the core conductor substantially free of an oxide. 17. An integrated circuit comprising: one or more active devices in a substrate; and a wiring structure coupled to at least one of the active devices, at least a portion of the wiring structure including: a first level via in a first insulator layer; a first conducting layer formed over and connecting to the first level via in the first insulator layer, the first conducting layer structured as two conductive layers; a core conductor disposed on and within the first conducting layer; and a capping layer disposed on and covering the core conductor and the first conducting layer, the capping layer being a conductor, the capping layer in contact with at least a center portion of the core conductor and a top portion of the. two conductive layers of the first conducting layer such that contact with the first conducting layer is limited to the top portion and inner surfaces of the first conducting layer, the inner surfaces containing the core conductor, the capping layer, the first conducting layer, and the core conductor being within a second insulator layer, the capping layer having at least one property from a group of an adhesion property and a barrier property, wherein an interface between the capping layer and the core conductor is substantially free of an oxide. 18. The integrated circuit of claim 17, wherein the two conductive layers are structured as a first layer and a seed layer, the first layer having at least one property from a group of an adhesion property and a barrier property. 19. The integrated circuit of claim 18, wherein the first layer includes a refractory metal, a compound of nitrogen and a tantalum alloy, or a compound of nitrogen and a tungsten alloy. 20. The integrated circuit of claim 17, wherein the core conductor includes copper, silver, a copper alloy, or a silver alloy. 21. The integrated circuit of claim 17, wherein the capping layer includes titanium, zirconium, hafnium, or nitrides of titanium, zirconium, or hafnium. 22. The integrated circuit of claim 17, wherein the capping layer has a thickness ranging from about 5 Å to about 40 Å. 23. The integrated circuit of claim 17, wherein the second insulator layer includes a polymer layer, a foamed polymer layer, or a fluorinated polymer layer. 24. The integrated circuit of claim 17, wherein the second insulator layer includes a polyimide layer, a foamed polyimide layer, or a fluorinated polyimide layer. 25. The integrated circuit of claim 17, wherein the second insulator layer includes an oxide layer, a fluorinated oxide layer, or an aerogel layer. 26. The integrated circuit of claim 17, wherein a top surface of the core conductor is substantially at a level with a top surface of the second insulator layer. 27. The integrated circuit of claim 17, further including a gap between two or more core conductors to provide an air bridge structure. 28. A memory device comprising: an array of memory cells in a substrate; and a wiring structure in the substrate coupling to the array of memory cells, at least a portion of the wiring structure including: a first level via in a first insulator layer; a first conducting layer formed over and connecting to the first level via in the first insulator layer, the first conducting layer structured as two conductive layers; a core conductor disposed on and within the first conducting layer; and a capping layer disposed on and covering the core conductor and the first conducting layer, the capping layer being a conductor, the capping layer in contact with at least a center portion of the core conductor and a top portion of the two conductive layers of the first conducting layer such that contact with the first conducting layer is limited to the top portion and inner surfaces of the first conducting layer, the inner surfaces containing the core conductor, the capping layer, the first conducting layer, and the core conductor being within a second insulator layer, the capping layer having at least one property from a group of an adhesion property and a barrier property, wherein an interface between the capping layer and the core conductor is substantially free of an oxide. 29. The memory device of claim 28, wherein the two conductive layers are structured as a first layer and a seed layer, the first layer having at least one property from a group of an adhesion property and a barrier property. 30. The memory device of claim 29, wherein the first layer includes a refractory metal, a compound of nitrogen and a tantalum alloy, or a compound of nitrogen and a tungsten alloy. 31. The memory device of claim 28, wherein the core conductor includes copper, silver, a copper alloy, or a silver alloy. 32. The memory device of claim 28, wherein the capping layer includes titanium, zirconium, hafnium, or nitrides of titanium, zirconium, or hafnium. 33. The memory device of claim 28, wherein the capping layer has a thickness ranging from about 5 Å to about 40 Å. 34. The memory device of claim 28, wherein the second insulator layer includes a polymer layer, a foamed polymer layer, or a fluorinated polymer layer. 35. The memory device of claim 28, wherein the second insulator layer includes a polyimide layer, a foamed polyimide layer, or a fluorinated polyimide layer. 36. The memory device of claim 28, wherein the second insulator layer includes an oxide layer, a fluorinated oxide layer, or an aerogel layer. 37. The memory device of claim 28, wherein a top surface of the core conductor is substantially at a level with a top surface of the second insulator layer. 38. An electronic system comprising: a controller; and one or more integrated circuits coupled to the controller, at least one integrated circuit having a wiring structure with at least a portion of the wiring structure including: an insulating layer; a conductive structure within the insulating layer, the conductive structure having: a first conducting layer structured as two conductive layers; a core conductor disposed on and within the first conducting layer; and a capping layer disposed on and covering the core conductor and the first conducting layer, the capping layer being a conductor, the capping layer in contact with at least a center portion of the core conductor and a top portion of the two conductive layers of the first conducting layer such that contact with the first conducting layer is limited to the top portion and inner surfaces of the first conducting layer, the inner surfaces containing the core conductor, the capping layer having at least one property from a group of an adhesion property and a barrier property, wherein an interface between the capping layer and the core conductor is substantially free of an oxide. 39. The electronic system of claim 38, wherein a top surface of the core conductor is substantially at a level with a top surface of the insulating layer. 40. The electronic system of claim 38, wherein the two conductive layers are structured as a first layer and a seed layer, the first layer having at least one property from a group of an adhesion property and a barrier property. 41. The electronic system of claim 40, wherein the first layer includes a refractory metal, a compound of nitrogen and a tantalum alloy, or a compound of nitrogen and a tungsten alloy. 42. The electronic system of claim 38, wherein the core conductor includes copper, silver, a copper alloy, or a silver alloy. 43. The electronic system of claim 38, wherein the capping layer includes titanium, zirconium, hafnium, or nitrides of titanium, zirconium, or hafnium. 44. The electronic system of claim 38 wherein the capping layer has a thickness ranging from about 5 Å to about 40 Å. 45. The electronic system of claim 38, wherein the insulating layer includes a polymer layer, a foamed polymer layer, or a fluorinated polymer layer. 46. The electronic system of claim 38, wherein the insulating layer includes a polyimide layer, a foamed polyimide layer, or a fluorinated polyimide layer. 47. The electronic system of claim 38, wherein the insulating layer includes an oxide layer, a fluorinated oxide layer, a silicon dioxide layer, or an aerogel layer. 48. The electronic system of claim 38, wherein the insulating layer is disposed on a dielectric structure having a via to connect to lower level metallizations or devices in a substrate. 49. The electronic system of claim 38, wherein the controller includes a processor. 50. The electronic system of claim 38, wherein the electronic system includes a computer.
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Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
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Sachdev Krishna Gandhi ; Hummel John Patrick ; Kamath Sundar Mangalore ; Lang Robert Neal ; Nendaic Anton ; Perry Charles Hampton ; Sachdev Harbans, Low TCE polyimides as improved insulator in multilayer interconnect structures.
Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
Keyser Thomas (Palm Bay FL) Cairns Bruce R. (Los Altos Hills CA) Anand Kranti V. (Sunnyvale CA) Petro William G. (Cupertino CA) Barry Michael L. (Palo Alto CA), Low temperature plasma nitridation process and applications of nitride films formed thereby.
Ahila Krishnamoorthy ; David J. Duquette ; Shyam P. Murarka, Metallization structures for microelectronic applications and process for forming the structures.
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Brors Daniel L. (Los Altos Hills CA) Fair James A. (Mountain View CA) Monnig Kenneth A. (Palo Alto CA), Method and apparatus for deposition of tungsten silicides.
Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
Omstead Thomas R. ; Wongsenakhum Panya ; Messner William J. ; Nagy Edward J. ; Starks William ; Moslehi Mehrdad M., Method and system for dispensing process gas for fabricating a device on a substrate.
Chen, Linlin; Wilson, Gregory J.; McHugh, Paul R.; Weaver, Robert A.; Ritzdorf, Thomas L., Method for electrochemically depositing metal on a semiconductor workpiece.
Svendsen Leo Gulvad (Redwood City CA) Walker Clifford James (Fremont CA) Lykins ; II James Leborn (San Jose CA), Method for electroplating a substrate containing an electroplateable pattern.
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Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
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Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
Fitzsimmons John A. (Poughkeepsie NY) Havas Janos (Hopewell Junction NY) Lawson Margaret J. (Newburgh NY) Leonard Edward J. (Fishkill NY) Rhoads Bryan N. (Pine Bush NY), Method for forming patterned films on a substrate.
Yang Tsung-Ju,TWX ; Wang Chien-Mei,TWX ; Kang Tsung-Kuei,TWX, Method for making intermetal dielectrics (IMD) on semiconductor integrated circuits using low dielectric constant spin-on polymers.
Chakravorty Kishore K. (Issaquah WA) Tanielian Minas H. (Bellevue WA), Method for producing a planar surface on which a conductive layer can be applied.
Lai Yeong-Chih,TWX ; Huang Chien-Chung,TWX ; Tsai Yu-Tai,TWX ; Wu Huang-Hui,TWX, Method for reducing critical dimension of dual damascene process using spin-on-glass process.
Wang Tsing-Chow (San Jose CA) Liang Louis H. (Los Altos CA), Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a tr.
van Laarhoven Josephus M. F. G. (Eindhoven NLX) de Bruin Leendert (Eindhoven NLX) van Arendonk Anton P. M. (Eindhoven NLX), Method of enabling electrical connection to a substructure forming part of an electronic device.
Durlam Mark ; Chen Eugene Youjun ; Tehrani Saied N. ; Slaughter Jon Michael ; Kerszykowski Gloria ; Kyler Kelly Wayne, Method of fabricating flux concentrating layer for use with magnetoresistive random access memories.
Steven C. Avanzino ; Kai Yang ; Sergey Lopatin ; Todd P. Lukanc, Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film.
Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
O'Neill Mark Leonard ; Robeson Lloyd Mahlon ; Burgoyne ; Jr. William Franklin ; Langsam Michael, Nanoporous polymer films for extreme low and interlayer dielectrics.
Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
Agnello Paul D. ; Buchwalter Leena P. ; Hummel John ; Luther Barbara ; Stamper Anthony K., Plasma treatment to enhance inorganic dielectric adhesion to copper.
Stevens E. Henry ; Berner Robert W., Process architecture and manufacturing tool sets employing hard mask patterning for use in the manufacture of one or more metallization levels on a workpiece.
Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
Paul A. Farrar, Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy.
Ping-Chuan Wang ; Ronald G. Filippi ; Robert D. Edwards ; Edward W. Kiewra ; Roy C. Iggulden, Process of enclosing via for improved reliability in dual damascene interconnects.
Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and h.
Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
Dennison Charles H. ; Doan Trung T., Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein.
Blalock Guy T. ; Howard Bradley J., Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures.
Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Semiconductor device having a low permittivity dielectric.
Xu Zheng ; Forster John ; Yao Tse-Yong, Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches.
Huang Richard J. (Milpitas CA) Hui Angela (Milpitas CA) Cheung Robin (Cupertino CA) Chang Mark (Los Altos CA) Lin Ming-Ren (Cupertino CA), Simplified dual damascene process for multi-level metallization and interconnection structure.
Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.
Cabral ; Jr. Cyril (Ossining NY) Colgan Evan G. (Suffern NY) Grill Alfred (White Plains NY), Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum.
Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
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