An apparatus for a network of computers is presented. A plurality of inner firewalls operate within a personal computer. The personal computer operates in a network of computers and includes at least one microprocessor and at least two memory components. The plurality of inner firewalls deny access
An apparatus for a network of computers is presented. A plurality of inner firewalls operate within a personal computer. The personal computer operates in a network of computers and includes at least one microprocessor and at least two memory components. The plurality of inner firewalls deny access to a first memory component of the personal computer by another computer through a network connection with the personal computer during a shared operation. The plurality of inner firewalls also allow access to a second memory component of the personal computer by the other computer through the network connection with the personal computer during the shared operation.
대표청구항▼
The invention claimed is: 1. A personal computer, comprising: a plurality of inner firewalls comprising at least one hardware component and/or at least one firmware component configured to operate within the personal computer, the personal computer being configured to operate in at least one networ
The invention claimed is: 1. A personal computer, comprising: a plurality of inner firewalls comprising at least one hardware component and/or at least one firmware component configured to operate within the personal computer, the personal computer being configured to operate in at least one network of computers, the personal computer comprising at least two microprocessors and at least two memory components, the at least two microprocessors being located on a single microchip; at least one of the plurality of inner firewalls being configured to deny access to at least one first microprocessor and at least one first memory component of the personal computer by at least one other computer through at least one network connection with the personal computer during at least one shared operation, and another at least one of the plurality of inner firewalls being configured to allow access to at least one second microprocessor and at least one second memory component of the personal computer by the at least one other computer through the at least one network connection with the at least one personal computer during the at least one shared operation. 2. The personal computer of claim 1, wherein at least one hardware component and/or software file, and/or firmware file is located within at least one of the plurality of inner firewalls. 3. The personal computer of claim 1, wherein the following are grouped together inside at least one of the plurality of inner firewalls: at least one hardware component and at least one software file; or at least one hardware component and at least one firmware file; or at least one software file and at least one firmware file; or at least one hardware component, at least one software file, and at least one firmware file. 4. The personal computer of claim 1, wherein at least one of the plurality of inner firewalls comprises at least one hardware component. 5. The personal computer of claim 1, further comprising at least one dense wave division multiplexing (DWDM) network connection. 6. The personal computer of claim 1, further comprising at least one device enabling at least one wireless network connection. 7. The personal computer of claim 6, further comprising at least one hardware encryption component. 8. The personal computer of claim 1, further comprising at least one operating system comprising more than one independent component, at least one of the more than one independent component having its own firewall. 9. The personal computer of claim 1, further comprising at least one operating system comprising more than one independent component, each independent component having its own firewall. 10. The personal computer of claim 1, further comprising at least one application program comprising more than one independent component, at least one of the more than one independent component having its own firewall. 11. The personal computer of claim 1 further comprising at least one application program comprising more than one independent component, each independent component having its own firewall. 12. The personal computer of claim 1, wherein all files of at least one network-accessible portion of volatile memory of the personal computer are erased when control of the at least one network-accessible portion is transferred between the at least one network of computers and at least one user of the personal computer, the at least one network-accessible portion being located outside at least one of the plurality of inner firewalls. 13. The personal computer of claim 12, wherein the volatile memory of the personal computer is erased by power interruption and/or overwriting. 14. The personal computer of claim of 1, wherein all files in at least one network-accessible portion of at least one non-volatile memory of the personal computer are erased when control of the at least one network-accessible portion is transferred between the at least one network and at least one user of the personal computer, the at least one network-accessible portion being located outside at least one of the plurality of inner firewalls. 15. The personal computer of claim 14, wherein the at least one of the plurality of inner firewalls is located on the single microchip. 16. The personal computer of claim 15, wherein at least one first memory component is located on the single microchip. 17. The personal computer of claim 15, wherein at least one second memory component is located on the single microchip. 18. The personal computer of claim 1, wherein the at least one first memory component comprises at least one system BIOS. 19. The personal computer of claim 1, wherein the single microchip has at least four or 8 or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors. 20. The personal computer of claim 19, wherein the single microchip comprises an at least one encryption component. 21. The personal computer of claim 19, wherein the single microchip comprises at least one field-programmable gate array (FPGA) and/or active configuration of an integrated circuit. 22. The personal computer of claim 19, wherein the single microchip comprises at least one master control and/or at least one processing microprocessor. 23. The personal computer of claim 1, wherein the at least one network of computers comprises the World Wide Web and/or the Internet. 24. The personal computer of claim 1, wherein the at least one network connection comprises at least one optical fiber connection directly to the personal computer. 25. The personal computer of claim 1, wherein the at least one first memory component is at least one flash memory device. 26. The personal computer of claim 1, wherein the at least one second memory component is at least one flash memory device. 27. The personal computer of claim 1, wherein the at least one second memory component is at least one random access memory (RAM) device. 28. The personal computer of claim 1, wherein the at least one second memory component is at least one hard drive device. 29. The personal computer of claim 1, wherein the at least one second memory component is at least one read-only compact disk drive (CD-ROM) device. 30. The personal computer of claim 1, wherein the at least one second memory component is at least one read-only digital video disk drive (DVD) device. 31. The personal computer of claim 1, wherein the at least one second memory component is volatile memory. 32. The personal computer of claim 1, wherein the at least one second memory component is non-volatile memory. 33. The personal computer of claim 32, wherein the non-volatile memory comprises at least one magnetic random access memory (MRAM) and/or ovonic memory. 34. The personal computer of claim 1, wherein the at least one first memory component is non-volatile memory. 35. The personal computer of claim 1, wherein the at least one second memory component duplicates the at least one first memory component. 36. The personal computer of claim 1, wherein the at least one first memory component is read and write memory. 37. The personal computer of claim 1, wherein the at least one second memory component is read-only memory. 38. The personal computer, comprising: a plurality of inner firewalls configured to operate within the personal computer, the personal computer being configured to operate in at least one network of computers, the personal computer comprising at least two microprocessors, at least one of the plurality of inner firewalls being configured to deny access to at least one first microprocessor of the personal computer by at least one other computer through at least one network connection with the personal computer during at least one shared operation, and another at least one of the plurality of inner firewalls being configured to allow access to at least one second microprocessor of the personal computer by the at least one other computer through the at least one network connection with the personal computer during the at least one shared operation. 39. The personal computer of claim 38, wherein at least one of the plurality of inner firewalls comprises at least one hardware component and/or at least one firmware component. 40. The personal computer of claim 39, wherein at least two or four or 8 or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors are located on a single microchip. 41. The personal computer of claim 40, wherein the single microchip comprises at least one encryption component. 42. The personal computer of claim 40, wherein the single microchip comprises at least one field-programmable gate array (FPGA) and/or active configuration of at least one integrated circuit. 43. The personal computer of claim 40, wherein the single microchip comprises at least one master control and/or at least one processing microprocessor. 44. The personal computer of claim 40, wherein the single personal computer comprises at least one device enabling at least one wireless network connection. 45. The personal computer of claim 38, wherein at least two of the plurality of inner firewalls and the at least two microprocessors are located on the single microchip. 46. The personal computer, comprising: at least one microchip comprising a plurality of inner firewalls configured to operate within the personal computer, the personal computer being configured to operate in at least one network of computers, at least one microchip comprising at least two microprocessors and at least two memory components, at least one of the plurality of inner firewalls being configured to deny access to at least one first microprocessor and at least one first memory component of the personal computer by at least one other computer through at least one network connection with the personal computer during at least one shared operation, and another at least one of the plurality of inner firewalls being configured to allow access to at least one second microprocessor and at least one second memory component of the personal computer by the at least one other computer through the at least one network connection with the personal computer during the at least one shared operation. 47. The personal computer of claim 46, wherein at least one of the plurality of inner firewalls comprises at least one hardware component and/or at least one firmware component. 48. The personal computer of claim 47, wherein at least two or four or 8 or 16 or 32 or 64 or 128 or 256 or 512 or 1024 microprocessors are located on a single microchip. 49. The personal computer of claim 48, wherein the single microchip comprises at least one encryption component. 50. The personal computer of claim 48, wherein the single microchip comprises at least one field-programmable gate array (FPGA) and/or active configuration of at least one integrated circuit. 51. The personal computer of claim 48, wherein the single microchip comprises at least one master control and/or at least one processing microprocessor. 52. The personal computer of claim 48, wherein the single personal computer comprises at least one device enabling at least one wireless network connection.
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Benkeser Donald E. (Naperville IL) Cyr Joseph B. (Aurora IL) Greenberg Albert G. (Millburn NJ) Wright Paul E. (Basking Ridge NJ), Adaptive job scheduling for multiprocessing systems with master and slave processors executing tasks with opposite antic.
Bonneau ; Jr. Walt C. (Missouri City TX) Guttag Karl (Missouri City TX) Gove Robert (Dallas TX), Architecture of a chip having multiple processors and multiple memories.
Russell David S. (Minneapolis MN) Fischer Larry G. (Waseca MN) Wala Philip M. (Waseca MN) Ratliff Charles R. (Crystal Lake IL) Brennan Jeffrey (Waseca MN), Cellular communications system with centralized base stations and distributed antenna units.
Naedel Richard G. (Rockville MD) Harris David B. (Columbia MD) Uehling Mark (Bowie MD), Chassis and personal computer for severe environment embedded applications.
Berkowitz David B. (Palo Alto CA) Hao Ming C. (Los Altos CA) Lieu Hung C. (Santa Clara CA) Snow Franklin D. (Saratoga CA), Collaborative computing system using pseudo server process to allow input from different server processes individually a.
Sumimoto Shinji (Kawasaki JPX), Computer resource distributing method and system for distributing a multiplicity of processes to a plurality of computer.
Passera Anthony ; Thorp John R. ; Beckerle Michael J. ; Zyszkowski Edward S. A., Computer system and computerized method for partitioning data for parallel processing.
Jones Oliver (Andover MA) Deshon Mary (Winthrop MA) Ericsson Staffan (Brookline MA) Flach James (Cave Creek AZ), Computer teleconferencing method and apparatus.
Glick James A. (Granite Shoals TX) Graczyk Ronald B. (Round Rock TX) Nurick Albert F. (Austin TX) Fraley Brittain D. (Austin TX), Computing and multimedia entertainment system.
Rosenberry Steven (Reading PA), Dynamic fault-tolerant parallel processing system for performing an application function with increased efficiency using.
Pian Chao-Kuang (Anaheim CA) Habereder Hans L. (Orange CA), Dynamic task allocation in a multi-processor system employing distributed control processors and distributed arithmetic.
Nguyen Tam M. (Valhalla NY) Rana Deepak (Yorktown Heights NY) Ruiz Antonio (Yorktown Heights NY) Willner Barry E. (Briarcliff Manor NY), Hybrid digital/analog multimedia hub with dynamically allocated/released channels for video processing and distribution.
Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
Ault Donald Fred ; Bender Ernest Scott ; Spiegel Michael Gary, Method and apparatus for creating a security environment for a user task in a client/server system.
Kisor Greg, Method and system including a central computer that assigns tasks to idle workstations using availability schedules and computational capabilities.
Rausch Dieter (Karlsruhe DEX), Method for preventing an overload when starting a multicomputer system and multicomputer system for carrying out said me.
Shorter David U. (Lewisville TX), Method for scheduling execution of distributed application programs at preset times in an SNA LU 6.2 network environment.
Harris Jonathan P. (Littleton MA) Leibholz Daniel (Watertown MA) Miller Brad (Westborough MA), Method of dynamically allocating processors in a massively parallel processing system.
Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.
Hodge Winston W. (Yorba Linda CA) Taylor Lawrence E. (Anaheim CA), Near-video-on-demand digital video distribution system utilizing asymmetric digital subscriber lines.
Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating one or more data processors linked together for parallel p.
Chin Danny (Robbinsville NJ) Sauer Donald J. (Allentown NJ) Meyerhofer Dietrich (Princeton NJ) Katsuki Kazuo (Hyogo JPX), Parallel digital processing system using optical interconnection between control sections and data processing sections.
Beatty Harry J. (Clinton Corners NY) Elmendorf Peter C. (Kingston NY) Gillis Roland R. (Ulster Park NY) Pramanick Ira (Wappingers Falls NY), Parallel execution of a complex task partitioned into a plurality of entities.
Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
Bahr James E. (Rochester MN) Corrigan Michael J. (Rochester MN) Knipfer Diane L. (Rochester MN) McMahon Lynn A. (Rochester MN) Metzger Charlotte B. (Elgin MN), Process for dispatching tasks among multiple information processors.
Nelson Darul J. ; Noval James V. ; Suarez Ricardo E. ; Aghazadeh Mostafa A., Processor card assembly including a heat sink attachment plate and an EMI/ESD shielding cage.
Gregerson Daniel P. ; Farrell David R. ; Gaitonde Sunil S. ; Ahuja Ratinder P. ; Ramakrishnan Krish ; Shafiq Muhammad ; Wallis Ian F., Scalable distributed computing environment.
Ohta Hiroyuki,JPX ; Miura Hideo,JPX ; Usami Mitsuo,JPX ; Kametani Masatsugu,JPX ; Zen Munetoshi,JPX ; Okamoto Noriaki,JPX, Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same.
Danahy John J. ; Kinney Daryl F. ; Pulsinelli Gary S. ; Rose Lawrence J. ; Kumar Navaneet, Service-centric monitoring system and method for monitoring of distributed services in a computing network.
Teper Jeffrey A. ; Koneru Sudheer ; Mangione Gordon ; Balaz Rudolph ; Contorer Aaron M. ; Chao Lucy, System and method for providing trusted brokering services over a distributed network.
Chasek Norman E. (24 Briar Brae Rd. Stamford CT 06903), System for developing real time economic incentives to encourage efficient use of the resources of a regulated electric.
Leclercq Thierry (Paris FRX) Sallio Patrick (Thorigne-Fouillard FRX), System for management of the usage of data consultations in a telecommunication network.
Choquier Philippe,FRX ; Peyroux Jean-Francios ; Griffin William J., System for on-line service in which gateway computer uses service map which includes loading condition of servers broad.
Kraft Reiner ; Lu Qi ; Wisebond Marat, Task distribution processing system and the method for subscribing computers to perform computing tasks during idle time.
Ellis, Frampton E., Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor.
Ellis, Frampton E., Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM.
Ellis, Frampton E., Computers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartments.
Ellis, III, Frampton E., Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.
Ellis, III, Frampton Erroll, Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.
Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.
Ellis, Frampton E., Computers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewalls.
Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Ellis, III, Frampton E., Microchips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the network.
Ellis, III, Frampton E., Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network.
Ellis, Frampton E., Personal computer, smartphone, tablet, or server with a buffer zone without circuitry forming a boundary separating zones with circuitry.
Preston, Dan; Preston, Joseph David; Blum, Rick Scott; Manos, Thomas August; Schofield, Kenneth, System and method for the configuration of an automotive vehicle with modeled sensors.
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