초록 ▼

A reconfigurable bit-manipulation node is disclosed that includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit is comprised of inte

A reconfigurable bit-manipulation node is disclosed that includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit is comprised of interconnected elements that include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.

대표청구항 ▼

What is claimed is: 1. A programmable data combiner comprising: a plurality of registers configured to receive a 16-bit or less input from a first source and a 5-bit or less input from a second source and to generate a first 20-bit or less output based on the 16-bit or less input from the first sou

What is claimed is: 1. A programmable data combiner comprising: a plurality of registers configured to receive a 16-bit or less input from a first source and a 5-bit or less input from a second source and to generate a first 20-bit or less output based on the 16-bit or less input from the first source and the 5-bit or less input from the second source; and a selector configured to receive a mode signal, a first set of one or more control signals capable of modifying an output word length, and the first 20-bit or less output and to select 4 bits or less from the first 20-bit or less output to generate a first selection of 4 bits or less based on the mode signal and the first set of one or more control signals; and a filler configured to receive and combine the 16-bit or less input from the first source, a 16-bit or less input from a third source, and the 4 bits or less selection output by the selector to generate a 32-bit or less output based on a second set of control signals capable of modifying an output word length. 2. The programmable data combiner of claim 1, wherein the plurality of registers is configured to perform a data packing operation when generating the 20-bit or less output based on the 16-bit or less input from the first source and the 5-bit or less input from the second source. 3. The programmable data combiner of claim 2, wherein the selector is configured to select and puncture bits from the first 20-bit or less output from the plurality of registers when generating the 4 bits or less selection based on the first set of control signals and the mode signal.