[특허]Temperature-compensated output buffer

Micron Technology, Inc.

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특허 상세정보

MyON담기

내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Temperature-compensated output buffer

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03K-017/16
미국특허분류(USC)	326/032; 326/030; 326/086
출원번호	US-0519697 (2006-09-11)
등록번호	US-7511531 (2009-03-31)
발명자 / 주소	Pan,Dong Janzen,Leel S.
출원인 / 주소	Micron Technology, Inc.
대리인 / 주소	TraskBritt
인용정보	피인용 횟수 : 4 인용 특허 : 15

초록
▼

A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal, forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal. Methods of operation, memory devices, semiconductor substrates and electronic systems embodying the invention are also disclosed.

대표
청구항
▼

What is claimed is: 1. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements, wherein the first supplemental circuit is in parallel with the first pull-up transistor and wherein the first supplemental output signal is a pull-up supplemental output signal configured to adjust a pull-up capability of the output buffer, and wherein the first supplemental circuit comprises a series-configured second pull-up transistor and a third pull-up transistor, the second and third pull-up transistors each controlled by one of the pull-up input signal and the first supplemental control signal. 2. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements, wherein the first supplemental circuit is in parallel with the first pull-up transistor and wherein the first supplemental output signal is a pull-up supplemental output signal configured to adjust a pull-up capability of the output buffer, and wherein the first supplemental circuit comprises a second pull-up transistor configured in parallel with the first pull-up transistor, the second pull-up transistor controlled in part by each of the pull-up input signal and the first supplemental control signal. 3. The output buffer of claim 2, further comprising: a third pull-up transistor controlled by the pull-up input signal and configured to pull up a gate input of the second pull-up transistor; and a fourth pull-up transistor controlled by the pull-up input signal and configured to pull up a gate input of the second pull-up transistor to a level of the first supplemental control signal. 4. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements, and wherein the first supplemental output signal is a pull-down supplemental output signal configured to adjust a pull-down capability of the output buffer, and wherein the first supplemental circuit comprises a series-configured second pull-down transistor and a third pull-down transistor, the second and third pull-down transistors each controlled by one of the pull-down input signal and the first supplemental control signal. 5. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements, and wherein the first supplemental output signal is a pull-down supplemental output signal configured to adjust a pull-down capability of the output buffer, and wherein the first supplemental circuit comprises a second pull-down transistor configured in parallel with the first pull-down transistor, the second pull-down transistor controlled in part by each of the pull-down input signal and the first supplemental control signal. 6. The output buffer of claim 5, further comprising: a third pull-down transistor controlled by the pull-down input signal and configured to pull down a gate input of the second pull-down transistor; and a fourth pull-down transistor controlled by the pull-down input signal and configured to pull down a gate input of the second pull-down transistor to a level of the first supplemental control signal. 7. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements and the output buffer further comprising a second supplemental circuit in parallel with the other one of the pull-up transistor or the pull-down transistor, the second supplemental circuit configured to generate, in response to a second supplemental control signal, a second supplemental output signal, the pull-up output signal, the pull-down output signal, the first supplemental output signal and the second supplemental output signal coupled to form the output buffer output signal; and wherein the second supplemental output signal is variable with temperature variation. 8. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements and the output buffer further comprising a biasing circuit for generating the pull-up control signal and the pull-down control signal for controlling the first supplemental circuit, wherein the biasing circuit is configured to generate the pull-up control signal as complementary to absolute temperature (CTAT). 9. An output buffer, comprising: a pull-up circuit including a pull-up transistor for providing a pull-up output signal responsive to a pull-up input signal; a pull-down circuit including a pull-down transistor for providing a pull-down output signal responsive to a pull-down input signal; a first supplemental circuit in parallel with one of the pull-up transistor or the pull-down transistor, the first supplemental circuit configured to generate, in response to a first supplemental control signal, a first supplemental output signal, the pull-up output signal, the pull-down output signal and the first supplemental output signal coupled to form an output buffer output signal; and wherein the first supplemental output signal is variable with temperature variation as determined by a comparison of electrical changes in temperature sensitive elements and the output buffer further comprising a biasing circuit for generating the pull-up control signal and the pull-down control signal for controlling the first supplemental circuit, wherein the biasing circuit is configured to generate the pull-down control signal as proportional to absolute temperature (PTAT).

이 특허에 인용된 특허 (15)

이 특허를 인용한 특허 피인용횟수: 4

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Temperature-compensated output buffer

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Temperature-compensated output buffer

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이 특허에 인용된 특허 (15)

이 특허를 인용한 특허 피인용횟수: 4

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