초록 ▼

A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the mem

A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.

대표청구항 ▼

The invention claimed is: 1. A method for providing positional read data latency in a cascaded interconnect memory subsystem, the method comprising: receiving a read request for a target memory module; calculating a delay period for the read request, with the delay period selected to prevent a coll

The invention claimed is: 1. A method for providing positional read data latency in a cascaded interconnect memory subsystem, the method comprising: receiving a read request for a target memory module; calculating a delay period for the read request, with the delay period selected to prevent a collision with other returned read data on a cascade interconnected bus used to communicate with the target memory module and an additional memory module, wherein the calculating of the delay period is responsive to one or more outstanding read commands previously issued to the memory subsystem and to a minimum read latency associated with the target memory module in consideration of the one or more outstanding read commands; transmitting a read command to the target memory module, the read command including the delay period, wherein the target memory module comprises one or more memory devices and one or more read data buffers to hold read data from the one or more memory devices corresponding to the read request; and receiving the read data at a memory controller from the target memory module in response to the read command via a cascade interconnected bus, wherein the target memory module has transmitted the read data to the memory controller after the delay period has expired. 2. The method of claim 1 wherein the one or more read data buffers hold the read data for a time specified by the delay period. 3. The method of claim 1 further comprising determining if the one or more read data buffers on the target memory module are available for holding the read data for the delay period specified by the read command, wherein the transmitting of the read command is executed in response to determining that the one or more read data buffers on the target memory module are available. 4. The method of claim 1 wherein the delay period is greater than zero. 5. The method of claim 1 wherein the delay period is equal to zero. 6. The method of claim 1 wherein the delay period is expressed in terms of data transfers. 7. The method of claim 1 wherein the delay period is expressed in terms of clock cycles.