초록 ▼

A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing po

A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.

대표청구항 ▼

What is claimed is: 1. A packet processing method for exchanging packet data through a plurality of layers recommended by an Open System Interconnection reference model, comprising: receiving a packet at a lower layer processing portion; storing, via the lower layer processing portion, the packet i

What is claimed is: 1. A packet processing method for exchanging packet data through a plurality of layers recommended by an Open System Interconnection reference model, comprising: receiving a packet at a lower layer processing portion; storing, via the lower layer processing portion, the packet into a packet memory; storing, via the lower layer processing portion, part of the packet used in processes performed by the lower layer processing portion and a higher layer processing portion into a multi-port shared memory, the lower layer processing portion and the higher layer processing portion accessing a same memory space of the multi-port shared memory via different memory buses; retrieving, via the higher layer processing portion, the part of the packet from the multi-port shared memory; processing, via the higher layer processing portion, the part of the packet to create an updated part; storing, via the higher layer processing portion, the updated part into the multi-port shared memory; retrieving, via the lower layer processing portion, the updated part from the multi-port shared memory; appending, via the lower layer processing portion, the updated part to the packet to create a new packet; and transmitting the new packet. 2. The packet processing method of claim 1 wherein the lower layer processing portion includes a layer 2 processing portion. 3. The packet processing method of claim 2 wherein the higher layer processing portion includes a layer 3 processing portion. 4. The packet processing method of claim 1 wherein the part of the packet includes a header portion of the packet. 5. The packet processing method of claim 1 wherein the storing a packet includes: storing the packet at a first memory location in the packet memory, and wherein the storing the part of the packet includes: storing the part of the packet in a second memory location in the multi-port shared memory, where the second memory location relates to the first memory location. 6. A device comprising: a packet memory to store a packet; a multi-port shared memory to store a part of the packet; a lower layer processing portion to: store the packet in the packet memory, store the part of the packet in the multi-port shared memory, and perform lower layer processing on the packet; and a higher layer processing portion to: read the part of the packet from the multi-port shared memory, and perform higher layer processing using the part of the packet, the lower layer processing portion and the higher layer processing portion accessing a same memory space of the multi-port shared memory via different memory buses. 7. The device of claim 6 wherein the multi-port shared memory includes a dual port memory. 8. The device of claim 6 wherein the packet memory includes a plurality of first memory spaces and the multi-port shared memory includes a plurality of second memory spaces, the plurality of second memory spaces corresponding to the plurality of first memory spaces. 9. The device of claim 6 wherein the lower layer processing portion includes a layer 2 processing portion. 10. The device of claim 9 wherein the higher layer processing portion includes a layer 3 processing portion. 11. The device of claim 6 wherein the part of the packet includes a header portion of the packet. 12. The device of claim 6 wherein, when storing the part of the packet in the multi-port shared memory, the lower layer processing portion is configured to: extract the part of the packet based on a protocol type of the higher layer processing portion or another higher layer processing portion, and store the extracted part of the packet in the multi-port shared memory. 13. The device of claim 6 wherein, when storing a part of the packet in the multi-port shared memory, the lower layer processing portion is configured to: extract a fixed length portion of the packet, and store the fixed length portion of the packet in the multi-port shared memory. 14. The device of claim 6 further comprising: a processor, connected to the lower layer processing portion and the higher layer processing portion, to execute a process at a layer higher than the higher layer processing. 15. A device comprising: a packet memory; a multi-port shared memory; a lower layer processing portion that connects to the multi-port shared memory via a first bus, the lower layer processing portion being configured to: store a packet in the packet memory, store a portion of the packet in the multi-port shared memory, and perform lower layer processing on the packet; and a higher layer processing portion that connects to the multi-port shared memory via a second bus, the second bus being different than the first bus, the higher layer processing portion being configured to: read the portion of the packet from the multi-port shared memory, and perform higher layer processing using the portion of the packet. 16. The device of claim 15 wherein the multi-port shared memory includes a dual port memory. 17. The device of claim 15 wherein the packet memory includes a plurality of first memory spaces and the multi-port shared memory includes a plurality of second memory spaces, the plurality of second memory spaces corresponding to the plurality of first memory spaces. 18. The device of claim 15 wherein the lower layer processing portion includes a layer 2 processing portion. 19. The device of claim 18 wherein the higher layer processing portion includes a layer 3 processing portion. 20. The device of claim 15 wherein the portion of the packet includes a header portion of the packet. 21. The device of claim 15 wherein, when storing a portion of the packet in the multi-port shared memory, the lower layer processing portion is configured to: extract the portion of the packet based on a protocol type of the higher layer processing portion or another higher layer processing portion, and store the extracted portion of the packet in the multi-port shared memory. 22. The device of claim 15 wherein, when storing a portion of the packet in the multi-port shared memory, the lower layer processing portion is configured to: extract a fixed length portion of the packet, and store the fixed length portion of the packet in the multi-port shared memory.