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Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-025/065
  • H01L-023/02
출원번호 UP-0939253 (2001-08-24)
등록번호 US-7518223 (2009-07-01)
발명자 / 주소
  • Derderian, James M.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 6  인용 특허 : 52

초록

A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement therewith

대표청구항

What is claimed is: 1. A semiconductor device for use in a stacked multi-chip assembly, comprising: a semiconductor die; and a dielectric spacer layer secured to at least a portion of a surface of the semiconductor die and protruding from the surface to space the semiconductor die substantially a p

이 특허에 인용된 특허 (52)

  1. Fogal Rich ; Ball Michael B., Angularly offset stacked die multichip device and method of manufacture.
  2. Tandy Patrick W., Assembling a stacked die package.
  3. Fee, Setho Sing; Chye, Lim Thiam; Heppler, Steven W.; Yin, Leng Nam; Tan, Keith; Guay, Patrick; Tian, Edmund Lua Koon; Eng, Yap Kah; Seng, Eric Tan Swee, Ball grid array interposer, packages and methods.
  4. Gordon Thomas A., Ball placement method and apparatus for forming a ball grid array.
  5. Salman Akram, Chip package with grease heat sink and method of making.
  6. Spielberger Richard K. ; Jensen Ronald J. ; Speerschneider Charles J., Chip stacking and capacitor mounting arrangement including spacers.
  7. Ball Michael B., Combination of semiconductor interconnect.
  8. Solberg Vernon, Compliant multichip package.
  9. Uchida Tatsuro (Yokohama JPX) Yebisuya Takashi (Tokyo JPX) Mori Miki (Yokohama JPX) Saito Masayuki (Yokohama JPX) Togasaki Takasi (Yokohama JPX) Kizaki Yukio (Yokohama JPX), Electronic circuit device.
  10. Doyle Brian S. ; Cheng Peng, Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition.
  11. Farnworth Warren M. ; Akram Salman, Interconnect for semiconductor components and method of fabrication.
  12. Smith ; Jr. Willis H. ; Erdmann John H. ; Reif Philip G., Liquid crystal light valves using internal, fixed spacers and method of incorporating same.
  13. Donald C. Foster, Making semiconductor devices having stacked dies with biased back surfaces.
  14. Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.
  15. Ma, Manny Kin F.; Bruce, Jeffrey D., Method for employing piggyback multiple die #3.
  16. Vindasius Alfons ; Robinson Marc E. ; Scharrenberg William R., Method for forming conductive epoxy flip-chip on chip.
  17. Mitchell, Craig; Warner, Mike; Behlen, Jim, Method for making a semiconductor chip package.
  18. Muff, Simon; Pohl, Jens; Winderl, Johann, Method for mounting a semiconductor chip on a carrier layer and device for carrying out the method.
  19. Schwiebert Matthew K. ; Campbell Donald T. ; Heydinger Matthew ; Kraft Robert E. ; Vander Plas Hubert A., Method of bumping substrates by contained paste deposition.
  20. Whalley Peter D. (23 ; Fairfields Great Kingshill ; Buckinghamshire ; HP15 6EP GB2) Evans Stephen D. (181 ; Ashford Avenue Hayes ; Middlesex ; UB4 OND ; GB2) Shaw John E. A. (45 ; Colne Avenue West D, Method of encapsulating a sensor device using capillary action and the device so encapsulated.
  21. Hayes Donald J. ; Hartnett Mary W., Method of forming an adhesive connection.
  22. Agarwala Birendra N. (Hopewell Junction NY) Ahsan Aziz M. (Hopewell Junction NY) Bross Arthur (Poughkeepsie NY) Chadurjian Mark F. (Essex Junction VT) Koopman Nicholas G. (Hopewell Junction NY) Lee L, Method of forming dual height solder interconnections.
  23. Chung Kevin Kwong-Tai, Method of forming fine-pitch interconnections employing a standoff mask.
  24. Hildering Willem C. (Eindhoven NLX), Method of providing spacers on an insulating substrate.
  25. Blanton James A. (Kokomo IN), Method of providing standoff pillars.
  26. Leonard Jay F. ; Chen Yanshu, Method of simultaneously attaching surface-mount and chip-on-board dies to a circuit board.
  27. Freyman Bruce J. (Plantation FL) Juskey Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL), Moisture relief for chip carrier.
  28. Chun Heung S. (Seoul KRX), Multi-chip semiconductor package.
  29. Ball Michael B., Multi-chip stacked devices.
  30. Fogal Rich (Boise ID) Ball Michael B. (Boise ID), Multichip module having a stacked chip arrangement.
  31. Lin Chun Hung,TWX, Multichip module having stacked chip arrangement.
  32. Foster, Donald C., Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring.
  33. Salman Akram, Multiple die stack apparatus employing T-shaped interposer elements.
  34. Mueller Peter,CHX ; Riel Heike E.,CHX ; Riess Walter,CHX ; Vestweber Horst,DEX, Organic opto-electronic devices.
  35. Randy H. Y. Lo TW; Chien-Ping Huang TW; Chi-Chuan Wu TW, Package structure stacking chips on front surface and back surface of substrate.
  36. Blanton James A. (Kokomo IN), Provision of substrate pillars to maintain chip standoff.
  37. Yamada Hiroyuki,JPX ; Hashimoto Masato,JPX ; Tsuda Seiji,JPX, Resistor and its manufacturing method.
  38. Johnson Gary Carl ; Anderson Michael J. ; Kennison Gregory Jon ; Christensen Jeffrey Eanes ; Popovich Mark Phillip, Saw device package and method.
  39. Hikita, Junichi; Nakatani, Goro; Kumamoto, Nobuhisa; Sameshima, Katsumi; Shibata, Kazutaka; Ueda, Shigeyuki, Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device.
  40. Nobuaki Hashimoto JP, Semiconductor device and manufacturing method thereof, circuit board and electronic equipment.
  41. Kurita, Yoichiro; Shironouchi, Toshiaki; Tetsuka, Takashi, Semiconductor device and method for manufacturing the same.
  42. Grigg, Ford B., Semiconductor device assemblies including interposers with dams protruding therefrom.
  43. Hirose Tatsuya,JPX, Semiconductor device face-down bonded with pillars.
  44. Fukui, Yasuki; Narai, Atsuya, Semiconductor device having insulation layer and adhesion layer between chip lamination.
  45. Sato Akira,JPX, Semiconductor package having enhanced ball grid array protective dummy members.
  46. Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package having substrate with laser-formed aperture through solder mask layer.
  47. Thomas P. Glenn ; Lee J. Smith ; David A. Zoba ; Kambhampati Ramakrishna ; Vincent DiCaprio, Semiconductor package including stacked semiconductor dies and bond wires.
  48. Shim, Il Kwon; Ramakrishna, Kambhampati; DiCaprio, Vincent, Semiconductor package with spacer strips.
  49. Cohn, David Leslie; McBride, Dennis Jay; Montoye, Robert Kevin, Spacer - connector stud for stacked surface laminated multichip modules and methods of manufacture.
  50. Pu, Han-Ping; Lo, Randy H. Y.; Her, Tzong-Dar; Huang, Chien-Ping; Hsiao, Cheng-Shiu; Wu, Chi-Chuan, Stacked-die package structure.
  51. Farnworth, Warren M.; Wood, Alan G., Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures.
  52. Love David G. (Pleasanton CA) Moresco Larry L. (San Carlos CA) Chou William Tai-Hua (Cupertino CA) Horine David A. (Los Altos CA) Wong Connie M. (Fremont CA) Beilin Solomon I. (San Carlos CA), Wire interconnect structures for connecting an integrated circuit to a substrate.

이 특허를 인용한 특허 (6)

  1. Ihara, Masaki; Shimizu, Hiroshi; Ito, Yoshinobu; Shimizu, Toshihiko; Tonouchi, Kenichi, Method of manufacturing polarizing plastic lens.
  2. Tan, Swee Seng Eric; Lee, Choon Kuan, Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice.
  3. Lee, Hsiao-Wen; Zung, Peter; Lin, Tzu-Han; Lin, Tzy-Ying; Chang, Chia-Yang; Lin, Chien-Pang, Optoelectronic device chip having a composite spacer structure and method making same.
  4. Seng, Eric Tan Swee; Kuan, Lee Choon, Semiconductor device assemblies including face-to-face semiconductor dice and related methods.
  5. Hufgard, Erich, Semiconductor wafer structure.
  6. Lam, Ken M., Stacked-die package including substrate-ground coupling.
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