초록 ▼

A channel encoding apparatus using a parallel concatenated low density parity check (LDPC) code. A first LDPC encoder generates a first component LDPC code according to information bits received. An interleaver interleaves the information bits according to a predetermined interleaving rule. A second

A channel encoding apparatus using a parallel concatenated low density parity check (LDPC) code. A first LDPC encoder generates a first component LDPC code according to information bits received. An interleaver interleaves the information bits according to a predetermined interleaving rule. A second LDPC encoder generates a second component LDPC code according to the interleaved information bits. A controller performs a control operation such that the information bits, the first component LDPC code which is first parity bits corresponding to the information bits, and the second component LDPC code which is second parity bits corresponding to the information bits are combined according to a predetermined code rate.

대표청구항 ▼

What is claimed is: 1. A channel encoding apparatus comprising: a first low density parity check (LDPC) encoder of generating a first component LDPC code according to information bits; an interleaver for interleaving the information bits according to an interleaving rule; a second LDPC encoder for

What is claimed is: 1. A channel encoding apparatus comprising: a first low density parity check (LDPC) encoder of generating a first component LDPC code according to information bits; an interleaver for interleaving the information bits according to an interleaving rule; a second LDPC encoder for generating a second component LDPC code according to the interleaved information bits; and a controller for performing a control operation so the information bits, the first component LDPC code, and the second component LDPC code are combined according to a code rate, wherein the interleaving rule is one of a plurality of interleaving rules comprising: a first interleaving rule set so variable nodes with a low degree in a factor graph of the first component LDPC code are mapped to variable nodes with a high degree in a factor graph of the second component LDPC code; a second interleaving rule set so variable nodes with a low degree in a factor graph of the second component LDPC code are mapped to variable nodes with a high degree in a factor graph of the first component LDPC code; a third interleaving rule set so variable nodes with a short mean cycle in a factor graph of the first component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the second component LDPC code; a fourth interleaving rule set so variable nodes with a short mean cycle in a factor graph of the second component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the first component LDPC code; a fifth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the first component LDPC code are mapped to variable nodes in a factor graph of the second component LDPC code so the variable nodes are included in different cycles in the factor graph of the second component LDPC code; and a sixth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the second component LDPC code are mapped to variable nodes in a factor graph of the first component LDPC code so the variable nodes are included in different cycles in the factor graph of the first component LDPC code, wherein a mean cycle is a value determined by dividing a sum of lengths of all cycles to which the variable nodes belong by a degree thereof, the short mean cycle is a mean cycle length less than or equal to a threshold mean cycle length, the long mean cycle is a mean cycle greater than the threshold mean cycle length, the short length is a cycle length less than or equal to a threshold cycle length, the low degree is a degree less than or equal to a threshold degree, and the high degree is a degree greater that the threshold degree. 2. The channel encoding apparatus of claim 1, wherein the first component LDPC is first parity bits corresponding to the information bits. 3. The channel encoding apparatus of claim 2, wherein the second component LDPC is first parity bits corresponding to the information bits. 4. A channel encoding method comprising: generating a first component low density parity check (LDPC) code according to information bits; interleaving the information bits according to an interleaving rule; generating a second component LDPC code according to the interleaved information bits; and performing a control operation so the information bits, the first component LDPC code, and the second component LDPC code are combined according to a code rate, wherein the interleaving rule is one of a plurality of interleaving rules comprising: a first interleaving rule set so variable nodes with a low degree in a factor graph of the first component LDPC code are mapped to variable nodes with a high degree in a factor graph of the second component LDPC code; a second interleaving rule set so variable nodes with a low degree in a factor graph of the second component LDPC code are mapped to variable nodes with a high degree in a factor graph of the first component LDPC code; a third interleaving rule set so variable nodes with a short mean cycle in a factor graph of the first component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the second component LDPC code; a fourth interleaving rule set so variable nodes with a short mean cycle in a factor graph of the second component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the first component LDPC code; a fifth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the first component LDPC code are mapped to variable nodes in a factor graph of the second component LDPC code so the variable nodes are included in different cycles in the factor graph of the second component LDPC code; and a sixth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the second component LDPC code are mapped to variable nodes in a factor graph of the first component LDPC code so the variable nodes are included in different cycles in the factor graph of the first component LDPC code, wherein a mean cycle is a value determined by dividing a sum of lengths of all cycles to which the variable nodes belong by a degree thereof, the short mean cycle is a mean cycle length less than or equal to a threshold mean cycle length, the long mean cycle is a mean cycle greater than the threshold mean cycle length, the short length is a cycle length less than or equal to a threshold cycle length, the low degree is a degree less than or equal to a threshold degree, and the high degree is a degree greater that the threshold degree. 5. The channel encoding method of claim 4, wherein the first component LDPC code is first parity bits corresponding to the information bits. 6. The channel encoding method of claim 4, wherein the second component LDPC code is second parity bits corresponding to the information bits. 7. A channel decoding apparatus comprising: a code rate controller for determining whether to use at least one of a first low density parity check (LDPC) decoder and a second LDPC decoder according to a code rate and a channel condition; a first LDPC decoder for generating a first component LDPC code upon receiving a first signal by decoding information updated during previous decoding, output from a second LDPC decoder, and information bits and first parity bits in the first received signal, and outputting the first component LDPC code to a first subtractor when the code rate controller determines to use both of the first LDPC decoder and the second LDPC decoder, or generating a first component LDPC code upon receiving a second signal by decoding information bits and first parity bits in the second received signal, and outputting the first component LDPC code to the code rate controller when the code rate controller determines to use the first LDPC decoder; the first subtractor for subtracting the updated information from a signal output from the first LDPC decoder; an interleaver for interleaving a signal output from the first subtractor according to an interleaving rule; the second LDPC decoder for generating a second component LDPC code by decoding a signal output from the interleaver and second parity bits in the first received signal; a second subtractor for subtracting a signal output from the interleaver from a signal output from the second LDPC decoder; a deinterleaver for deinterleaving a signal output from the second subtractor according to a deinterleaving rule corresponding to the interleaving rule, and outputting the deinterleaved signal to the first LDPC decoder and the first subtractor; a controller for controlling the interleaving rule and deinterleaving rule, wherein the code rate controller outputs the signal output from the first LDPC decoder as final decode bits when the code rate controller determines to use the first LDPC decoder, and the code rate controller controls that second LDPC decoder outputs the second component LDPC code as final decode bits when the code rate controller determines to use both of the first decoder and the second decoder. 8. The channel decoding apparatus of claim 7, wherein the interleaving rule is one of a plurality of interleaving rules comprising: a first interleaving rule set so variable nodes with a low degree in a factor graph of the first component LDPC code are mapped to variable nodes with a high degree in a factor graph of the second component LDPC code; a second interleaving rule set so variable nodes with a low degree in a factor graph of the second component LDPC code are mapped to variable nodes with a high degree in a factor graph of the first component LDPC code; a third interleaving rule set so variable nodes with a short mean cycle in a factor graph of the first component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the second component LDPC code; a fourth interleaving rule set so variable nodes with a short mean cycle in a factor graph of the second component LDPC code arc mapped to variable nodes with a long mean cycle in a factor graph of the first component LDPC code; a fifth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the first component LDPC code are mapped to variable nodes in a factor graph of the second component LDPC code so the variable nodes are included in different cycles in the factor graph of the second component LDPC code; and a sixth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the second component LDPC code are mapped to variable nodes in a factor graph of the first component LDPC code so the variable nodes are included in different cycles in the factor graph of the first component LDPC code; wherein a mean cycle is a value determined by dividing a sum of lengths of all cycles to which the variable nodes belong by a degree thereof, the short mean cycle is a mean cycle length less than or equal to a threshold mean cycle length, the long mean cycle is a mean cycle greater than the threshold mean cycle length, the short length is a cycle length less than or equal to a threshold cycle length, the low degree is a degree less than or equal to a threshold degree, and the high degree is a degree greater that the threshold degree. 9. A channel decoding apparatus comprising: a first low density parity check (LDPC) encoder of generating a first component LDPC code according to information bits; an interleaver of interleaving the information bits according to an interleaving rule; a second LDPC encoder of generating a second component LDPC code according to the interleaved information bits; and a controller of performing a control operation so the information bits, the first component LDPC code, and the second component LDPC code are combined according to a code rate, wherein the interleaving rule is one of a plurality of interleaving rules comprising: a first interleaving rule set so variable nodes with a low degree in a factor graph of the first component LDPC code are mapped to variable nodes with a high degree in a factor graph of the second component LDPC code; a second interleaving rule set so variable nodes with a low degree in a factor graph of the second component LDPC code are mapped to variable nodes with a high degree in a factor graph of the first component LDPC code; a third interleaving rule set so variable nodes with a short mean cycle in a factor graph of the first component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the second component LDPC code; a fourth interleaving rule set so variable nodes with a short mean cycle in a factor graph of the second component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the first component LDPC code; a fifth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the first component LDPC code are mapped to variable nodes in a factor graph of the second component LDPC code so the variable nodes are included in different cycles in the factor graph of the second component LDPC code; and a sixth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the second component LDPC code are mapped to variable nodes in a factor graph of the first component LDPC code so the variable nodes are included in different cycles in the factor graph of the first component LDPC code, wherein a mean cycle is a value determined by dividing a sum of lengths of all cycles to which the variable nodes belong by a degree thereof, the short mean cycle is a mean cycle length less than or equal to a threshold mean cycle length, the long mean cycle is a mean cycle greater than the threshold mean cycle length, the short length is a cycle length less than or equal to a threshold cycle length, the low degree is a degree less than or equal to a threshold degree, and the high degree is a degree greater that the threshold degree. 10. A channel decoding method comprising: generating a first component low density parity check (LDPC) code for a first reception signal upon receiving the first reception signal by decoding information updated during previous decoding, and information bits and first parity bits in the first reception signal when a code rate R2 is used in a channel coding apparatus, or generating a first component LDPC code for a second reception signal upon receiving the second reception signal by decoding information bits and first parity bits in the second reception signal when a code rate R1 is used in the channel coding apparatus; subtracting the updated information from the first component LDPC code for the first reception signal; interleaving a signal acquired by subtracting the updated information from the first component LDPC code for the first reception signal according to an interleaving rule; generating a second component LDPC code by decoding the interleaved signal and second parity bits in the first reception signal; subtracting the interleaved signal from the second component LDPC code; deinterleaving a signal acquired by subtracting the interleaved signal from the second component LDPC code according to a deinterleaving rule corresponding to the interleaving rule; and outputting one of the first component LDPC code for the second reception signal and the second component LDPC code as final decoded bits according to a code rate and a channel condition. 11. The channel decoding method of claim 10, wherein the interleaving rule is one of a plurality of interleaving rules comprising: a first interleaving rule set so variable nodes with a low degree in a factor graph of the first component LDPC code are mapped to variable nodes with a high degree in a factor graph of the second component LDPC code; a second interleaving rule set so variable nodes with a low degree in a factor graph of the second component LDPC code are mapped to variable nodes with a high degree in a factor graph of the first component LDPC code; a third interleaving rule set so variable nodes with a short mean cycle in a factor graph of the first component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the second component LDPC code; a fourth interleaving rule set so variable nodes with a short mean cycle in a factor graph of the second component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the first component LDPC code; a fifth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the first component LDPC code are mapped to variable nodes in a factor graph of the second component LDPC code so the variable nodes are included in different cycles in the factor graph of the second component LDPC code; and a sixth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the second component LDPC code are mapped to variable nodes in a factor graph of the first component LDPC code so the variable nodes are included in different cycles in the factor graph of the first component LDPC code; wherein a mean cycle is a value determined by dividing a sum of lengths of all cycles to which the variable nodes belong by a degree thereof, the short mean cycle is a mean cycle length less than or equal to a threshold mean cycle length, the long mean cycle is a mean cycle greater than the threshold mean cycle length, the short length is a cycle length less than or equal to a threshold cycle length, the low degree is a degree less than or equal to a threshold degree, and the high degree is a degree greater that the threshold degree. 12. A channel decoding method comprising: generating a first component low density parity check (LDPC) code for a first reception signal upon receiving the first reception signal by decoding information updated during previous decoding, and information bits and first parity bits in the first received signal when a code rate R2 is used in a channel coding apparatus, or generating a first component LDPC code for a second reception signal upon receiving the second reception signal by decoding information bits and first parity bits in the second reception signal when a code rate R1 is used in the channel coding apparatus; subtracting the updated information from the first component LDPC code for the first reception signal; interleaving a signal acquired by subtracting the updated information from the first component LDPC code for the first reception signal according to an interleaving rule; generating a second component LDPC code by decoding the interleaved signal and second parity bits in the first reception signal; subtracting the interleaved signal from the second component LDPC code; deinterleaving a signal acquired by subtracting the interleaved signal from the second component LDPC code according to a deinterleaving rule corresponding to the interleaving rule; and outputting one of the first component LDPC code for the second reception signal and the second component LDPC code as final decoded bits according to a code rate; wherein the interleaving rule is one of a plurality of interleaving rules comprising: a first interleaving rule set so variable nodes with a low degree in a factor graph of the first component LDPC code are mapped to variable nodes with a high degree in a factor graph of the second component LDPC code; a second interleaving rule set so variable nodes with a low degree in a factor graph of the second component LDPC code are mapped to variable nodes with a high degree in a factor graph of the first component LDPC code; a third interleaving rule set so variable nodes with a short mean cycle in a factor graph of the first component LDPC code arc mapped to variable nodes with a long mean cycle in a factor graph of the second component LDPC code; a fourth interleaving rule set so variable nodes with a short mean cycle in a factor graph of the second component LDPC code are mapped to variable nodes with a long mean cycle in a factor graph of the first component LDPC code; a fifth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the first component LDPC code are mapped to variable nodes in a factor graph of the second component LDPC code so the variable nodes are included in different cycles in the factor graph of the second component LDPC code; and a sixth interleaving rule set so variable nodes constituting a cycle with a short length in a factor graph of the second component LDPC code are mapped to variable nodes in a factor graph of the first component LDPC code so the variable nodes are included in different cycles in the factor graph of the first component LDPC code, wherein a mean cycle is a value determined by dividing a sum of lengths of all cycles to which the variable nodes belong by a degree thereof, the short mean cycle is a mean cycle length less than or equal to a threshold mean cycle length, the long mean cycle is a mean cycle greater than the threshold mean cycle length, the short length is a cycle length less than or equal to a threshold cycle length, the low degree is a degree less than or equal to a threshold degree, and the high degree is a degree greater that the threshold degree.