Process for manufacturing wafers usable in the semiconductor industry
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/30
H01L-021/02
C03C-015/00
출원번호
UP-0607802
(2006-12-01)
등록번호
US-7524736
(2009-07-01)
우선권정보
EP-05425885(2005-12-14)
발명자
/ 주소
Ottaviani, Giampiero
Corni, Federico
Ferrari, Paolo
Villa, Flavio Francesco
출원인 / 주소
STMicroelectronics S.r.l.
대리인 / 주소
Jorgenson, Lisa K.
인용정보
피인용 횟수 :
5인용 특허 :
6
초록▼
To manufacture a layer of semiconductor material, a first wafer of semiconductor material is subjected to implantation to form a defect layer at a distance from a first face; the first wafer is bonded to a second wafer, by putting an insulating layer present on the second wafer in contact with the f
To manufacture a layer of semiconductor material, a first wafer of semiconductor material is subjected to implantation to form a defect layer at a distance from a first face; the first wafer is bonded to a second wafer, by putting an insulating layer present on the second wafer in contact with the first face of the first wafer. Then, hydrogen atoms are introduced into the first wafer through a second face at an energy such as to avoid defects to be generated in the first wafer and at a temperature lower than 600° C. Thereby, the first wafer splits into a usable layer, bonded to the second wafer, and a remaining layer disposed between the defect layer and the second face of the first wafer. Prior to bonding, the first wafer is subjected to processing steps for obtaining integrated components.
대표청구항▼
The invention claimed is: 1. A process for manufacturing a layer of semiconductor material, comprising, in sequence: providing a first wafer of semiconductor material having a first face and a second face; forming a defect layer in said first wafer at a distance from said first face; bonding said f
The invention claimed is: 1. A process for manufacturing a layer of semiconductor material, comprising, in sequence: providing a first wafer of semiconductor material having a first face and a second face; forming a defect layer in said first wafer at a distance from said first face; bonding said first face of said first wafer to a second wafer; and introducing atomic hydrogen into said first wafer through said second face at an energy such as to avoid defects to be generated in said first wafer and at a temperature lower than 600° C., causing the separation of said first wafer into a usable layer bonded to said second wafer and a remaining layer comprised between said defect layer and said second face. 2. The process according to claim 1, wherein, prior to said bonding, providing electronic components integrated in and on top of said first wafer in proximity of said first face. 3. The process according to claim 1, wherein said forming a defect layer comprises implanting ion species such as to generate defects within said first wafer and carrying out a first thermal process. 4. The process according to claim 3, wherein said ion species are chosen in the group comprising Si, Ge, Ne, Ar, As, and P. 5. The process according to claim 3, wherein said implanting is carried out at a dose comprised between 1013 and 1016 atoms/cm2, preferably between 1 and 15 atoms/cm2. 6. The process according to claim 3, wherein said first thermal process comprises carrying out a rapid thermal process at temperatures comprised between 1200° C. and 800° C., preferably between 1100° C. and 700° C. 7. The process according to claim 1, wherein said bonding comprises forming an insulating layer on one of said first and second wafers and putting said first wafer in contact with second wafer through said insulating layer. 8. The process according to claim 7, wherein, after the bonding, a second stabilization annealing is carried out at a temperature of between 200° C. and 600° C., typically between 200° C. and 400° C. 9. The process according to claim 1, wherein said atomic hydrogen has an energy lower than 50 eV, preferably lower than 10 eV. 10. The process according to claim 1, wherein introducing atomic hydrogen is carried out at a temperature lower than 500° C., preferably comprised between 300° C. and 400° C. 11. The process according to claim 1, further comprising: providing a third wafer of semiconductor material having a first face and a second face; forming a defect layer in said third wafer, at a distance from said first face thereof; bonding said first face of said third wafer to said usable layer; and introducing atomic hydrogen into said third wafer through said second face of said third wafer at an energy such as to avoid defects to be generated in said third wafer and at a temperature lower than 600° C., causing separation of said third wafer into an active layer bonded to said usable layer and a discard layer. 12. The process according to claim 1, further comprising providing MEMS components in said usable layer. 13. A process for manufacturing wafers, comprising: implanting one or more dopant species in a wafer; performing a thermal process to remove at least some defects in the wafer, forming a defect-reduced region demarcated from a bulk region by a defect boundary; and introducing hydrogen atoms through the bulk region, wherein the defect boundary prevents at least some of the hydrogen atoms from entering the defect-reduced region. 14. The process of claim 13, wherein the defect boundary prevents a majority of the hydrogen atoms from entering the defect-reduced region. 15. The process of claim 13, further comprising integrating electronic components in or on top of the defect-reduced region. 16. The process of claim 13, wherein a sufficient amount of the hydrogen atoms accumulate along the defect boundary, causing the defect-reduced region to separate from the bulk region at the defect boundary. 17. The process of claim 16, wherein the hydrogen atoms have an energy level that enables the sufficient amount of the hydrogen atoms to reach the defect boundary without being trapped by defects at one or more locations other than the defect boundary. 18. The process of claim 16, wherein the hydrogen atoms are introduced at an energy level that is at most 50 eV. 19. The process of claim 16, wherein the hydrogen atoms are introduced at an energy level that is at most 10 eV. 20. The process of claim 13, wherein the one or more dopant species are selected from a group of elements comprising group 14, group 15, and group 18. 21. The process of claim 13, wherein the one or more dopant species comprise one of more of Si, Ge, Ne, Ar, As, and P. 22. The process of claim 13, wherein the defect-reduced region is a first defect-reduced region, and wherein the process further comprises: implanting one or more second dopant species in a second wafer; performing a second thermal process to remove at least some second defects in the second wafer, forming a second defect-reduced region demarcated from a second bulk region by a second defect boundary; bonding the first and second defect-reduced regions; and introducing hydrogen atoms through the second bulk region, causing the second defect-reduced region to separate from the second bulk region at the second defect boundary. 23. A process for manufacturing a layer of semiconductor material, comprising: forming a defect boundary within a first wafer, wherein the defect boundary demarcates a usable region of the first wafer from a bulk region of the first wafer; bonding the usable region to a second wafer; and introducing hydrogen atoms through the bulk region, wherein the defect boundary prevents at least some of the hydrogen atoms from entering the usable region. 24. The process of claim 23, wherein the defect boundary prevents a majority of the hydrogen atoms from entering the usable region. 25. The process of claim 23, wherein the defect boundary is formed, at least partially, by: implanting one or more dopant species in the first wafer, the one or more dopant species comprising one of more of Si, Ge, Ne, Ar, As, and P; and performing a thermal process to remove at least some defects in the first wafer. 26. The process of claim 25, wherein the thermal process is a rapid thermal process performed at temperatures between 700° C. and 1100° C. 27. The process of claim 23, further comprising, before bonding the usable region to the second wafer: integrating electronic components in or on top of the usable region; and covering a surface of the usable region with a passivation layer. 28. The process of claim 27, wherein the passivation layer comprises a silicon-oxide layer. 29. The process of claim 23, wherein the hydrogen atoms are introduced at an energy level that is at most 50 eV. 30. The process of claim 23, wherein the hydrogen atoms are introduced at an energy level that is at most 10 eV.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (6)
Henley Francois J. ; Cheung Nathan, Controlled cleavage process using pressurized fluid.
Carr, William; Usenko, Alexander, Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer.
Schulze, Hans-Joachim; Rodriguez, Francisco Javier Santos; Mauder, Anton; Baumgartl, Johannes; Ahrens, Carsten, Method for manufacturing a semiconductor device.
Schulze, Hans-Joachim; Santos Rodriguez, Francisco Javier; Mauder, Anton; Baumgartl, Johannes; Ahrens, Carsten, Method for manufacturing a semiconductor device by thermal treatment with hydrogen.
Nakajima, Tsunehiro, Wafer support system and method for separating support substrate from solid-phase bonded wafer and method for manufacturing semiconductor device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.