A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. A video scaling system preferably conserves memory by downscaling video prior to captu
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. A video scaling system preferably conserves memory by downscaling video prior to capturing the video in memory and upscaling video after the video is called out of memory.
대표청구항▼
The invention claimed is: 1. A video scaler, comprising: an input for receiving a video image; clock-selection circuitry that receives a video input clock and a display output clock and selects one of the video input clock and the display output clock for upscaling and one of the video input clock
The invention claimed is: 1. A video scaler, comprising: an input for receiving a video image; clock-selection circuitry that receives a video input clock and a display output clock and selects one of the video input clock and the display output clock for upscaling and one of the video input clock and the display output clock for downscaling of the video image; a scaler engine capable of both downscaling the video image to generate a first scaled video image and upscaling the video image to generate a second scaled video image, the scaler engine using the clock selected by the clock-selection circuitry; a memory capable of storing the video image or the first scaled video image; and means for determining whether the video image is to be downscaled or upscaled. 2. The video scaler of claim 1, comprising: first means capable of receiving the video image to be upscaled from the input, receiving the first scaled video image from the scaler engine, and providing the video image to be upscaled or the first scaled video image to the memory; second means capable of recieving the video image to be downscaled from the input, recieving the video image to be upscaled from the memory, and providing the video imagetobedownscaledorthevideoimagetobeupscaledto the scaler engine; and third means capable of recieving the first scaled video image from the memory, recieving the second scaled video image from the scaler engine, and outputting either the first scaled video image or the second scaled video image. 3. The video scaler of claim 2, comprising fourth means capable of recieving and selecting between a digital video image and a digitized analog video image, and the fourth means outputs the selected one of the digital video image and the digitized analog video image as the video image. 4. The video scaler of claim 1, wherein the scaler engine downscales the video image using the video input clock. 5. The video scaler of claim 1, wherein the scaler engine upscales the video image using the display output clock. 6. The video scaler of claim 1, comprising a plurality of line buffers for providing the video image to the input. 7. The video scaler of claim 1, wherein the scaler engine comprises a horizontal scaler and a vertical scaler. 8. The video scaler of claim 1, wherein the scaler engine is a single physical device that is logically in both an upscale path and a downscale path of the video image. 9. A video scaler, comprising: clock-selection circuitry that receives a video input clock and a display output clock and selects one of the video input clock and the display output clock for upscaling and one of the video input clock and the display output clock for downscaling of a video image a scaler engine capable of both downscaling the video image to generate a first scaled video image and upscaling the video image to generate a second scaled video image, the scaler engine using the clock selected by the clock-selection circuitry and the video image received via an input of the video scaler; a memory capable of storing the video image or the first scaled video image; and one or both of circuitry and/or code that determines whether the video image is to be downscaled or upscaled. 10. The video scaler of claim 9, wherein said one or both of said circuitry and/or code receives the video image to be upscaled from the input, receives the first scaled video image from the scaler engine, and provides the video image to be upscaled or the first scaled video image to the memory. 11. The video scaler of claim 9, wherein said one or both of said circuitry and/or code receives the video image to be downscaled from the input, receives the video image to be upscaled from the memory, and provides the video image to be downscaled or the video image to be upscaled to the scaler engine. 12. The video scaler of claim 9, wherein said one or both of said circuitry and/or code receives the first scaled video image from the memory, receives the second scaled video image from the scaler engine, and outputs either the first scaled video image or the second scaled video image. 13. The video scaler of claim 9, wherein said one or both of said circuitry and/or code receives and selects between a digital video image and a digitized analog video image, said at least one circuitry outputs the selected one of the digital video image and the digitized analog video image as the video image. 14. The video scaler of claim 9, wherein the scaler engine downscales the video image using the video input clock. 15. The video scaler of claim 9, wherein the scaler engine upscales the video image using the display output clock. 16. The video scaler of claim 9, comprising a plurality of line buffers for providing the video image to the input. 17. The video scaler of claim 9, wherein the scaler engine comprises a horizontal scaler and a vertical scaler. 18. The video scaler of claim 9, wherein the scaler engine is a single physical device that is logically in both an upscale path and a downscale path of the video image. 19. A video scaler, comprising: an input for receiving a video image; a scaler engine capable of both downscaling the video image to generate a first scaled video image and upscaling the video image to generate a second scaled video image, the scaler engine using a clock selected between a video input clock and a display output clock; a memory capable of storing the video image or the first scaled video image; and means for determining whether the video image is to be downscaled or upscaled, wherein the scaler engine comprises a horizontal scaler and a vertical scaler, and wherein one or both of the horizontal scaler and the vertical scaler comprises a programmable filter. 20. A method for processing video data, the method comprising: receiving a video image by a video scaling engine; determining whether the video scaling engine requires less memory space to scale the video image before writing the video image to memory or after reading the video image from the memory; scaling the received video image based on the determination; and if the video scaling engine requires less memory space to scale the video image before writing the video image to the memory: scaling the video image in the video scaling engine using a video input clock of the video scaling engine to generate a first scaled video image; writing the first scaled video image to the memory; reading the first scaled video image from the memory; outputting the first scaled video image; and blending the first scaled video image with a graphics image to generate a blended video and graphics image. 21. A method for processing video data, the method comprising: receiving a video image by a video scaling engine; determining whether the video scaling engine requires less memory space to scale the video image before writing the video image to memory or after reading the video image from the memory; scaling the received video image based on the determination; if the video scaling engine requires less memory space to scale the video image before writing the video image to the memory: scaling the video image in the video scaling engine using a video input clock of the video scaling engine to generate a first scaled video image; writing the first scaled video image to the memory; reading the first scaled video image from the memory; and outputting the first scaled video image; and if the video scaling engine requires less memory space to scale the video image after reading the video image from the memory: writing the video image to the memory prior to scaling; reading the video image from the memory; scaling the video image in the video scaling engine using a display output clock of the video scaling engine to generate a second scaled video image; outputting the second scaled video image; and blending the second scaled video image with a graphics image to generate a blended video and graphics image 22. A method for processing video data, the method comprising: receiving a video image by a video scaling engine; determining whether the video scaling engine requires less memory bandwidth to scale the video image before writing the video image to memory or after reading the video image from the memory; scaling the received video image based on the determination; if the video scaling engine requires less memory bandwidth to scale the video image before writing the video image to the memory: scaling the video image in the video scaling engine using a video input clock of the video scaling engine to generate a first scaled video image; writing the first scaled video image to the memory; reading the first scaled video image from the memory; and outputting the first scaled video image; and if the video scaling engine requires less memory bandwidth to scale the video image after reading the video image from the memory: writing the video image to the memory prior to scaling; reading the video image from the memory; scaling the video image in the video scaling engine using a display output clock of the video scaling engine to generate a second scaled video image; and outputting the second scaled video image, wherein scaling the video image using the display output clock comprises upscaling the video image. 23. A video scaler, comprising: a scaler engine capable of both downscaling a video image to generate a first scaled video image and upscaling the video image to generate a second scaled video image, the scaler engine using a clock selected between a video input clock and a display output clock, and the video image received via an input of the video scaler; a memory capable of storing the video image or the first scaled video image; and one or both of circuitry and/or code that determines whether the video image is to be downscaled or upscaled, wherein the scaler engine comprises a horizontal scaler and a vertical scaler, and wherein at least one of the horizontal scaler and the vertical scaler comprises a programmable filter.
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Murphy Nicholas J. N.,GBX, 3D graphics object copying with reduced edge artifacts.
Kunkel Gerard ; Krisbergh Harold ; Grosky Aaron ; Lee Jae Hea Edward ; Augenbraun Joseph E., Access system and method for providing interactive access to an information source through a networked distribution syst.
Bunker William M. (Ormond Beach FL) Chandler Jimmy E. (Holly Hill FL) Economy Richard (Ormond Beach FL) Fadden ; Jr. Richard G. (Daytona Beach FL) Nelson Michael P. (Ormond Beach FL), Advanced video object generator.
Priem Curtis (Freemont CA) Webber Thomas (Lynn MA) Malachowsky Chris (Santa Clara CA), Anti-aliasing raster operations utilizing sub-pixel crossing information to control pixel shading.
Sabella Paolo (Pleasanton CA) Evans Jerald R. (Mountain View CA) Johnson Deron (Newalk CA), Apparatus and method for managing the assignment of display attribute identification values and multiple hardware color.
Greaves Paul E. (Rancho Cordova CA) Moore Michael R. (Folsom CA) Perlman Stephen G. (Mountain View CA) Thompson Laurence A. (Saratoga CA), Apparatus and method for merging input RGB and composite video signals to provide both RGB and composite merged video ou.
Cooper J. Carl (Monte Sereno CA) Wallen David (San Francisco CA) Vojnovic Mirko (Santa Clara CA) Loveless Howard (Ben Lomond CA), Apparatus and method for synchronizing asynchronous signals.
Drako Dean M. (Los Altos CA) Yu Hsin-Tung A. (Palo Alto CA), Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memor.
Iwase Toshihiro (Nara JPX) Kanekura Hiroshi (Yamatokouriyama JPX), Apparatus for and method of converting a sampling frequency according to a data driven type processing.
Siracusa Robert J. (Lawrenceville NJ) Zdepski Joel W. (Belle Mead NJ), Apparatus for excising (and reinserting) specific data from a compressed video data stream to reduce its transmission ba.
Drako Dean M. (Los Altos CA) Yu Hsiu-Tung A. (Palo Alto CA), Apparatus for manipulating image pixel streams to generate an output image pixel stream in response to a selected mode.
Clough Elizabeth A. (Menlo Park CA) Roskowski Steven G. (Sunnyvale CA) Perlman Stephen G. (Mountain View CA) Masterson Anthony D. (Cupertino CA), Apparatus for providing output filtering from a frame buffer storing both video and graphics signals.
Ciacelli Mark Louis ; Urda John William ; Lam Wai Man ; Kouloheris Jack Lawrence ; Fetkovich John Edward, Apparatus, method and computer program product for protecting copyright data within a computer system.
Nally Robert M. (Plano TX) Schafer John C. (Wylie TX), Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems.
Gerard Chauvel FR; Serge Lasserre FR; Mario Giani FR; Tiemen Spits ; Gerard Benbassat FR; Frank L. Laczko, Sr. ; Y. Paul Chiang ; Karen L. Walker ; Mark E. Paley ; Brian O. Chae, Audio and video decoder circuit and system.
Bates Cary L. (Rochester MN) Cragun Brian J. (Rochester MN) Donovan Robert J. (Rochester MN) Jaaskelainen William (Oronoco MN) Ryan Jeffrey M. (Byron MN) Striemer Bryan L. (Zumbrota MN), Aural position indicating mechanism for viewable objects.
Childers Jim (Fort Bend TX) Reinecke Peter (Lockhart TX) Takahashi Yutaka (Ushiku JPX) Yamamoto Seiichi (Ibaragi JPX), Circuitry and method for performing two operating instructions during a single clock in a processing device.
Larson Michael Kerry ; McDonald Timothy James, Circuits systems and methods for managing data requests between memory subsystems operating in response to multiple address formats.
Marlton Anthony P. (Essex GBX) Fielder Dennis A. (Cambridge GBX) Halstead ; deceased Victor G. (late of Essex GBX by Susan Halstead ; administrator ) Stockill Trevor R. (Essex GBX), Computer based display system allowing mixing and windowing of graphics and video.
Walsh Bruce E. ; Herdrich John ; Smith William ; Vrabel Mark E. ; Borghesani Philip ; Hagberg Christine G. ; Champagne Karen, Computer based video system.
Gulick Dale ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system and method for transferring commands and data to a dedicated multimedia engine.
Mergard James Oliver ; Quimby Michael S. ; Wakeland Carl K., Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU.
Gulick Dale E. ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having a dedicated multimedia engine and multimedia memory having arbitration logic which grants main me.
Melo Maria L. ; Deschepper Todd ; Wilson Jeffrey T., Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base.
Gulick Dale E. ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having separate digital and analog system chips for improved performance.
Salbaum Helmut,DEX ; Bauer Harald,DEX ; Fruhwald Friedrich,DEX, D.M.A. controller that determines whether the mode of operation as either interrupt or D.M.A. via single control line.
Childers Jim (Fort Bend TX) Takahashi Yutaka (Ushiku JPX), Data transfer control circuit with a sequencer circuit and control subcircuits and data control method for successively.
Boyce Jill M. (Manalapan NJ) Pearlstein Larry (Newton PA), Digital video decoder for decoding digital high definition and/or digital standard definition television signals.
Watts LaVaughn F. (Houston TX) Smith Ronald L. (Houston TX) Pandya Yogendra C. (Houston TX) Wood Paul B. (Houston TX), Display system with multiple scrolling regions.
Werner Ross G. (Woodside CA) Ryherd Eric L. (Brookline NH), Drawing processor for computer graphic system using a plurality of parallel processors which each handle a group of disp.
Blahut Donald E. (Holmdel NJ) Szurkowski Edward S. (Maplewood NJ), Electronic circuits for the graphical display of overlapping windows with transparency.
Disanto Frank J. (North Ills NY) Krusos Denis A. (Lloyd Harbor NY) Laspina Christopher (Syosset NY), Electrophoretic display employing gray scale capability utilizing area modulation.
Alexander G. MacInnis ; Chengfuh Jeffrey Tang ; Xiaodong Xie ; James T. Patterson ; Greg A. Kranawetter, Graphics display system with color look-up table loading mechanism.
MacInnis Alexander G. ; Tang Chengfuh Jeffrey ; Xie Xiaodong ; Patterson James T. ; Kranawetter Greg A., Graphics display system with unified memory architecture.
Dye, Thomas A.; Geiger, Peter D.; Alvarez, II, Manuel J., Graphics system and method for rendering independent 2D and 3D objects using pointer based display list video refresh operations.
Michael F. Deering, Graphics system having a super-sampled sample buffer with generation of output pixels using selective adjustment of filtering for reduced artifacts.
Van Hook Timothy J. ; Cheng Howard H. ; DeLaurier Anthony P. ; Gossett Carroll P. ; Moore Robert J. ; Shepard Stephen J. ; Anderson Harold S. ; Princen John ; Doughty Jeffrey C. ; Pooley Nathan F. ; , High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing.
Pfeiffer David M. (Plano TX) Stoner David T. (McKinney TX) Norsworthy John P. (Carrollton TX) Dipert Dwight D. (Richardson TX) Thompson Jay A. (Plano TX) Fontaine James A. (Plano TX) Corry Michael K., High speed image processing computer with overlapping windows-div.
Shibata Hideaki (Osaka JPX) Bannai Tatsushi (Sakai JPX), High-efficiency coding apparatus for compressing a digital video signal while controlling the coding bit rate of the com.
Lum Sanford S.,CAX ; Chen Keping,CAX ; Wong Samuel L. C.,CAX ; Bennett Dwayne R.,CAX ; Alford Michael A.,CAX, Host CPU independent video processing unit.
Borrel Paul ; Cheng Keh-Shin Fu ; Menon Jai Prakash ; Rossignac Jaroslaw Roman, Hotlinks between an annotation window and graphics window for interactive 3D graphics.
O\Connor Michael (11127 Palos Verdes Dr. Cupertino CA 95014) Nemirovsky Mario D. (5999 W. Walbrook Dr. San Jose CA 95129), Image composition method and apparatus for developing, storing and reproducing image data using absorption, reflection a.
Miyuki Enokida JP; Tadashi Yoshida ; Kunihiro Yamamoto JP, Information processing method and apparatus for displaying a list of a plurality of image data files and a list of search results.
Rhodes Kenneth E. (Portland OR) Adams Robert T. (Lake Oswego OR) Janes Sherman (Portland OR) Coelho Rohan G. F. (Hillsboro OR), Integrated graphics and video computer display system.
Fandrianto Jan ; Martin Bryan R. ; Neubauer Doug G. ; Tran Duat H. ; Cressa Matthew D. ; Soemedi Arijanto, Integrated multimedia communications processor and codec.
Crochiere Ronald Eldon (Chatham NJ) Rabiner Lawrence Richard (Berkeley Heights NJ), Interpolation-decimation circuit for increasing or decreasing digital sampling frequency.
Nachtergaele Lode J.M.,BEX ; Catthoor Francky,BEX ; Kapoor Bhanu ; Janssens Stefan,BEX, Low power video decoder system with block-based motion compensation.
Carini Richard P. (Kingston NY) Donnelly James A. (West Hurley NY) Ellis ; Jr. Joseph J. (West Hurley NY) Lanzoni Thomas P. (Kingston NY), Merged data storage panel display.
Jouppi Norman P. ; McCormack Joel J. ; Chang Chun-Fa, Method and apparatus for compositing colors of images with memory constraints for storing pixel data.
Rhodes Ken (Portland OR) Coelho Rohan (Hillsboro OR) Frank Davis (Beaverton OR) Bender Blake (Beaverton OR), Method and apparatus for displaying an image in a windowed environment.
Gough Michael L. (Ben Lomond CA) Venolia Daniel S. (Foster City CA) Gilley Thomas S. (Pleasanton CA) Robbins Greg M. (Cupertino CA) Hansen ; Jr. Daniel J. (Cupertino CA) Oswal Abhay (Fremont CA) Tam , Method and apparatus for displaying an overlay image.
Dilliplane Stephen C. ; Lavelle Gary J. ; Maino James G. ; Selvaggi Richard J. ; Tseng Jack, Method and apparatus for displaying multiple windows on a display monitor.
Allen John Lewis ; Cross Leonard W. ; Munson Bill A. ; Oztaskin Ali S. ; Traylor Roger, Method and apparatus for draining video data from a planarized video buffer.
Mills Karl Scott ; Holmes Jeffrey Michael ; Bonnelycke Mark Emil ; Owen Richard Charles Andrew, Method and apparatus for executing a raster operation in a graphics controller circuit.
Staggs Kevin P. (Glendale AZ) Clarke ; Jr. Charles J. (Phoenix AZ) Huntington James C. (Phoenix AZ), Method and apparatus for filling polygons displayed by a raster graphic system.
Kelley Michael W. (San Mateo CA) Yen Shou-Chern (Sunnyvale CA), Method and apparatus for incremental acceleration of the rendering process utilizing multiple scanline rendering devices.
Garrison John Michael ; Wilson Gale Arthur, Method and apparatus for manipulating very long lists of data displayed in a graphical user interface using a layered li.
Edward H. Frank ; Patrick J. Naughton ; James Arthur Gosling ; John C. Liu, Method and apparatus for presenting information in a display system using transparent windows.
Gough Michael L. ; MacDougald Joseph J. ; Venolia Daniel S. ; Gilley Thomas S. ; Robbins Greg M. ; Hansen ; Jr. Daniel J. ; Oswal Abhay, Method and apparatus for providing translucent images on a computer display.
Chow Paul,CAX ; Mizuyabu Carl K.,CAX ; Swan Philip L.,CAX ; Porter Allen J.C.,CAX ; Wang Chun,CAX, Method and apparatus for storing and displaying video image data in a video graphics system.
Lee William Robert ; Rumph Darryl Jonathan, Method and apparatus for synchronizing video and graphics data in a multimedia display system including a shared frame b.
Gebler Charlene Ann ; Ngai Agnes Yee ; Vachon Michael Patrick ; Woodard Robert Leslie, Method and apparatus to accommodate partial picture input to an MPEG-compliant encoder.
Jenison Timothy P. (6237 SW. 23rd St. Topeka KS 66614), Method and apparatus utilizing look-up tables for color graphics in the digital composite video domain.
Batson James (Sunnyvale CA) Beernink Ernie (Mountain View CA) Fung David (Cupertino CA) Potel Michael (Los Altos Hills CA) Cabral Art (Mountain View CA) Clark Cary (San Jose CA), Method for building a color look-up table.
Yokota Teppei (Chiba JPX) Aramaki Junichi (Chiba JPX) Kihara Nobuyuki (Tokyo JPX), Method of recording on a recording medium employing an automatic updating of management data by monitoring the signal be.
Sporer Michael ; Kline Mark H. ; Zawojski Peter, Motion video processing circuit for capture playback and manipulation of digital motion video information on a computer.
King Sherman T. (San Francisco CA) Lee Tommy C. (Danville CA) Wang Niantsu (Milpitas CA) Chu Yen-Fah (San Jose CA) Kimura Scott A. (San Jose CA) Hwang Guorjuh T. (Milpitas CA), Multimedia overlay system for graphics and video.
Foster, Eric M.; Franklin, Dennis E.; Lam, Wai Man; Losinger, Raymond E.; Ngai, Chuck H., Processing errors in MPEG data as it is sent to a fixed storage device.
Cottle Temple D. ; Spits Tiemen T., Programmable interrupt controller with interrupt set/reset register and dynamically alterable interrupt mask for a single interrupt processor.
Ogrinc Michael A. (San Francisco CA) Card Robert A. (Palo Alto CA) Burns Chris R. (Mountain View CA) Clarke Charles P. (Los Altos CA) Collier Ronda L. (Scotts Valley CA) Collins Kevin M. (San Mateo C, Real time video image processing system.
Slattery William ; Gratacap Regis, Remultipelxer cache architecture and memory organization for storing video program bearing transport packets and descriptors.
Clark Gordon R. ; Myers George H. ; Gagliardi Louis R. ; Tavallaei Siamak, Server controller configured to snoop and receive a duplicative copy of display data presented to a video controller.
Anderson ; Jr. Bruce J. ; Lamont Nadine ; Drasner Sharyn L. ; Greenberg Arthur L., Set top terminal for an interactive information distribution system.
Thomas McGee ; Nevenka Dimitrova ; Jan Herman Elenbaas, Significant scene detection and frame filtering for a visual indexing system using dynamic thresholds.
Fielder Dennis (Linton GBX) Derbyshire James (Willingham GBX) Gillingham Peter (Kanata CAX) Torrance Randy (Ottawa CAX) O\Connell Cormac (Kanata CAX), Single chip frame buffer and graphics accelerator.
Crinon Regis J. ; Sezan Muhammed Ibrahim, Sprite-based video coding system with automatic segmentation integrated into coding and sprite building processes.
Ke Ligang ; Lutz Juergen M., System and method for utilizing a two-dimensional adaptive filter for reducing flicker in interlaced television images converted from non-interlaced computer graphics data.
Baker Richard T. ; Pipho Randall E., System for controlling data packet transfers by associating plurality of data packet transfer control instructions in packet control list including plurality of related logical functions.
Priem Curtis ; Rosenthal David S. H., System for providing fast transfers to input/output device by assuring commands from only one application program reside in FIFO.
Volk Patrick Michael (Kirkland WA) Robin Michael Breed (Redmond WA) Thorne ; III Edwin (Seattle WA) Kapell JoGene (Bellevue WA), Systems and methods for a customizable sprite-based graphical user interface.
Chung Moo-Taek,KRX ; Childers Jim ; Miyaguchi Hiroshi,JPX ; Becker Manfred,DEX, Timing and control circuit and method for a synchronous vector processor.
Washington Emanuel ; Perkins Mike ; Johnson Brian ; How Stephen ; Daines Nolan ; Ayers Tom ; Vertrees Keith, Transport stream decoder/demultiplexer for hierarchically organized audio-video streams.
Timothy J. Van Hook ; Howard H. Cheng ; Anthony P. DeLaurier ; Carroll P. Gossett ; Robert J. Moore ; Stephen J. Shepard ; Harold S. Anderson ; John Princen ; Jeffrey C. Doughty ; Nathan F. , Video game system and coprocessor for video game system.
Reinert Christopher L. (Plano TX) Sharma Sudhir (Plano TX) Nally Robert M. (Plano TX) Schafer John C. (Wylie TX), Video processing apparatus systems and methods.
Abe Keiko,JPX ; Yanase Koji,JPX, Video signal processing device that facilitates editing by producing control information from detected video signal information.
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