Nonvolatile semiconductor memory device
원문보기
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
UP-0878039
(2007-07-20)
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등록번호 |
US-7539040
(2009-07-01)
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우선권정보 |
JP-2006-206678(2006-07-28) |
발명자
/ 주소 |
- Tamai, Yukio
- Sawa, Akihito
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출원인 / 주소 |
- Sharp Kabushiki Kaisha
- Institute of Advanced Industrial Science and Technology
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
8 인용 특허 :
4 |
초록
▼
A nonvolatile semiconductor memory device comprises a memory cell including a variable resistance element changing its electric resistance by voltage application and having current-voltage characteristics in which a positive bias current flowing when a positive voltage is applied from one electrode
A nonvolatile semiconductor memory device comprises a memory cell including a variable resistance element changing its electric resistance by voltage application and having current-voltage characteristics in which a positive bias current flowing when a positive voltage is applied from one electrode as a reference electrode to the other electrode through an incorporated rectifier junction is larger than a negative bias current, a memory cell selection circuit for selecting the memory cell from the memory cell array, a voltage supply circuit for supplying a voltage to the memory cell so that a predetermined positive voltage corresponding to the reading operation is applied to the other electrode of the variable resistance element, in the reading operation, and a readout circuit for detecting the amount of the positive bias current and reading the information stored in the selected memory cell, in order to suppress the reading disturbance of the memory cell.
대표청구항
▼
What is claimed is: 1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a row direction and a column direction, the memory cell including a variable resistance element having a laminated structure comprising a rectifier junc
What is claimed is: 1. A nonvolatile semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a row direction and a column direction, the memory cell including a variable resistance element having a laminated structure comprising a rectifier junction showing rectifying characteristics in current-voltage characteristics and two electrodes for applying a voltage to the rectifier junction, the variable resistance element exhibiting current-voltage characteristics so that a positive bias current flowing when a positive voltage is applied based on one of the two electrodes as a reference electrode to the other electrode is larger than a negative bias current flowing when a negative voltage is applied to the other electrode, the current-voltage characteristics is asymmetric with respect to a voltage polarity applied to the other electrode, the variable resistance element being capable of storing information by a change of an electric resistance due to voltage application between the two electrodes; a memory cell selection circuit for selecting the memory cell from the memory cell array by the row, column or memory cell; a voltage supplying circuit for supplying a predetermined voltage according to a writing operation and reading operation, to one or more selected memory cells selected by the memory cell selection circuit through the memory cell selection circuit; and a readout circuit for reading the information stored in the selected memory cell by detecting the amount of a reading current flowing in accordance with a voltage applied to the variable resistance element of the selected memory cell and a resistance state of the variable resistance element in the reading operation for the selected memory cell, wherein the memory cell selection circuit and the voltage supplying circuit apply a predetermined positive voltage according to the reading operation based on the reference electrode to the other electrode in the variable resistance element of the selected memory cell, and the readout circuit detects the amount of the positive bias current flowing from the other electrode to the reference electrode to read the information stored in the selected memory cell, in the reading operation for the selected memory cell. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell selection circuit selects the memory cell from the memory cell array by the row or column. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises the variable resistance element only, and the memory cell array comprises a plurality of row selection lines extending in a row direction and a plurality of column selection lines extending in a column direction, and each of the memory cells in the same row is connected at one end of the variable resistance element to the same row selection line, and each of the memory cells in the same column is connected at the other end of the variable resistance element to the same column selection line. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises a series circuit including the variable resistance element and a cell-access transistor, and the memory cell array comprises a plurality of row selection lines extending in a row direction and a plurality of column selection lines extending in a column direction, each of the memory cells in the same row is connected at a gate of the cell-access transistor to the same row selection line, each of the memory cells in the same column is connected at one end of the series circuit to the same column selection line, and each of the memory cells is connected at the other end of the series circuit to a source line, and the memory cell selection circuit selects at least one from the memory cells in the same row in the memory cell array. 5. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises a series circuit including the variable resistance element and a cell-access diode, and the memory cell array comprises a plurality of row selection lines extending in a row direction and a plurality of column selection lines extending in a column direction, each of the memory cells in the same row is connected at one end of the series circuit to the same row selection line, and each of the memory cells in the same column is connected at the other end of the series circuit to the same column selection line, and the memory cell selection circuit selects at least one from the memory cells in the same row or column in the memory cell array. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the rectifier junction is a schottky junction. 7. The nonvolatile semiconductor memory device according to claim 1, wherein the rectifier junction is a p-n junction. 8. The nonvolatile semiconductor memory device according to claim 1, wherein the rectifier junction is a hetero junction. 9. The nonvolatile semiconductor memory device according to claim 8, wherein the hetero junction is a p-n junction. 10. The nonvolatile semiconductor memory device according to claim 8, wherein the hetero junction comprises semiconductors having the same conductivity type. 11. The nonvolatile semiconductor memory device according to claim 1, wherein at least one of two materials constituting the rectifier junction is a perovskite-type metal oxide. 12. The nonvolatile semiconductor memory device according to claim 1, wherein the two materials constituting the rectifier junction are a perovskite-type metal oxide.
이 특허에 인용된 특허 (4)
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Krieger, Juri H.; Yudanov, Nikolai, Memory device with active passive layers.
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Kawai Shinji,JPX ; Kobayashi Shinichi,JPX ; Taito Yasuhiko,JPX, Non-volatile semiconductor memory device having large margin of readout operation for variation in external power supply.
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Sarin,Vishal; Tran,Hieu Van; Frayer,Jack, Read bitline inhibit method and apparatus for voltage mode sensing.
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Ooishi, Tsukasa, Semiconductor memory device reading data based on memory cell passing current during access.
이 특허를 인용한 특허 (8)
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Azuma, Ryotaro; Shimakawa, Kazuhiko, Cross-point variable resistance nonvolatile memory device.
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Chang, Kuo-Pin; Lue, Hang-Ting, Diode memory.
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You, Wen-Chun; Tu, Kuo-Chi; Chang, Chih-Yang; Chen, Hsia-Wei; Liao, Yu-Wen; Yang, Chin-Chieh; Shih, Sheng-Hung; Chu, Wen-Ting, Memory cells breakdown protection.
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Edahiro, Toshiaki; Kanda, Kazushige; Tokiwa, Naoya; Futatsuyama, Takuya; Hosono, Koji; Ohshima, Shigeo, Non-volatile memory device and method for writing data thereto.
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Edahiro, Toshiaki; Kanda, Kazushige; Tokiwa, Naoya; Futatsuyama, Takuya; Hosono, Koji; Ohshima, Shigeo, Non-volatile memory device and method for writing data thereto.
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Awaya, Nobuyoshi; Tamai, Yukio; Sawa, Akihito, Nonvolatile semiconductor memory device.
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Johnson, Adam D., Resistive memory sensing methods and devices.
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Choi, Hyun-sik; Kim, Ho-jung; Jeong, Hyung-su, Resistor devices and digital-to-analog converters using the same.
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