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Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/24
  • G06F-013/20
출원번호 UP-0329470 (2006-01-05)
등록번호 US-7543096 (2009-07-01)
발명자 / 주소
  • Davies, Ian Robert
출원인 / 주소
  • Dot Hill Systems Corporation
대리인 / 주소
    Davis, E. Alan
인용정보 피인용 횟수 : 9  인용 특허 : 46

초록

A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU. The CPU fetches and executes pro

대표청구항

I claim: 1. A fault-tolerant mass storage system, comprising: first and second RAID controllers, coupled for communication via a PCI-Express link, each comprising: a bus bridge, coupled to said link and to first and second buses; a cache memory, coupled to said first bus, configured to cache user d

이 특허에 인용된 특허 (46)

  1. Jeddeloh,Joseph, Accelerated graphics port for a multiple memory controller computer system.
  2. Surugucchi Krishnakumar Rao ; George Geeta, Apparatus and method for coupling devices to a PCI-to-PCI bridge in an intelligent I/O controller.
  3. Okazawa Koichi (Tokyo JPX) Kimura Koichi (Yokohama JPX) Kawaguchi Hitoshi (Yokohama JPX) Aburano Ichiharu (Hitachi JPX) Kobayashi Kazushi (Ebina JPX) Mochida Tetsuya (Yokohama JPX), Bus system for use with information processing apparatus.
  4. Pecone, Victor Key, Bus zoning in a channel independent storage controller architecture.
  5. DeKoning Rodney A. ; Hoglund Timothy E., Centralized management of resources shared by multiple processing units.
  6. Harriman, David, Communicating transaction types between agents in a computer system using packet headers including an extended type/extended length field.
  7. Busser, Richard W.; Davies, Ian R., Data mirroring using shared buses.
  8. Brian Arsenault ; Victor W. Tung ; Jeffrey Stoddard Kinne, Data storage system.
  9. Tawfik David A. (Woodcliff Lake NJ) Doniger Jerry (Montvale NJ) Porawski Donald J. (Cedar Grove NJ), Digital flight guidance system.
  10. Sgammato, Frank J., Dynamic port mode selection for crosspoint switch.
  11. Tim Teitenberg ; Bikram Singh Bakshi, Efficient memory management for channel drivers in next generation I/O system.
  12. Olarig Sompong Paul, Failover memory for a computer system.
  13. Nielson Michael E. (Broomfield CO) Brant William A. (Boulder CO) Neben Gary (Boulder CO), Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a m.
  14. Shaffer Robert G. (New Britain PA), Frequency-to-binary converter.
  15. Abraham Menachem (Lexington MA) Bartolini David (Dudley MA) Ben-Meir Samuel (Sharon MA) Carmi Ilan (Framingham MA) Cook ; III John L. (Southborough MA) Hart Ira (Cambridge MA) Herman Alex (Sharon MA), Generic backplane system which is configurable to serve different network access methods simultaneously.
  16. Bandera Daniel Quinto ; Legband Dale Arthur, Hot spare light weight mirror for raid system.
  17. Corrigan Brian E. ; Rymph Alan D., Inter-bus bridge circuit with integrated memory port.
  18. Esterberg, Dennis R; Dickie, James P, Interchangeable and configurable input/output module for a computing deviceco.
  19. Shek Edde Tang Tin ; Stubbs Robert E., Interrupt mechanism on NorthBay.
  20. Yang,Kent YingKuang; Goodwin,William Patrick, Lock and release mechanism for out-of-order frame prevention and support of native command queueing in FC-SATA.
  21. Chan Jong, Memory controller supporting redundant synchronous memories.
  22. Lau Winnie K. W. (Shapin HKX) Malinowski Richard (Placerville CA), Memory partitioning.
  23. Bashford, Patrick R., Message signaled interrupt generating device and method.
  24. Rinaldis,Joseph M.; Ghaffari,Bahareh, Method and apparatus for improved RAID 1 write performance in low cost systems.
  25. Schneider Randy D. (Spring TX) Flower David L. (Tomball TX), Method and apparatus for improving the performance of partial stripe operations in a disk array subsystem.
  26. Rahman Monis ; Poplingher Mircea ; Yeh Tse-Yu ; Chen Wenliang, Method and apparatus for performing reads of related data from a set-associative cache memory.
  27. Pettey,Christopher J.; Khan,Asif; Pagan,Annette; Pekkala,Richard E.; Utley,Robert Haskell, Method and apparatus for shared I/O in a load/store fabric.
  28. Harris, Kenneth M., Method and apparatus for updating data in mass storage subsystem using emulated shared memory.
  29. Gary William Batchelor ; Carl Evan Jones ; Forrest Lee Wade, Method and system for perfetching data in a bridge system.
  30. Swanstrom Scott, Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA control.
  31. Gregg Thomas A. (Highland NY) Capowski Robert S. (Verbank NY) Ferraiolo Frank D. (New Windsor NY) Halma Marten J. (Poughquag NY) Hillock Thomas H. (Woodstock NY) Murray Robert E. (Kingston NY), Method for transferring data between processors on a network by establishing an address space for each processor in each.
  32. Aaron W. Ogus, Methods and protocol for simultaneous tuning of reliable and non-reliable channels of a single network communication link.
  33. Pecone Victor Key ; Swanson Dwayne Howard, Modular bus bridge system compatible with multiple bus pin configurations.
  34. Jibbe Mahmoud K. (Wichita KS) McCombs Craig C. (Wichita KS) Thompson Kenneth J. (Wichita KS), Multiple configuration data path architecture for a disk array controller.
  35. Liron Moshe (Evanston IL), Peripheral unit controller.
  36. Islam Shah Mohammad Rezaul ; Oza Bharatkumar Jayantilal, RAID system having a selectable unattended mode of operation with conditional and hierarchical automatic re-configuration.
  37. Suzuki Akira,JPX, Radio communication system in which base station transmits signal indicating whether or not message is valid to termina.
  38. Lui Albert S. ; Naminski Ronald John ; Oliver James Wesley ; Aster Radek ; Wood Neill Preston, Raid system with fibre channel arbitrated loop.
  39. Young Paul R. (Cromwell CT) Solari Peter L. (Lebanon CT) Shumski Gregory J. (Colchester CT) So Yin Cheung (Fremont CA), Redundant array of solid state memory devices.
  40. Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
  41. Crockett Robert N. (Tucson AZ) Kern Ronald M. (Tucson AZ) Micka William F. (Tucson AZ), Software directed microcode state save for distributed storage controller.
  42. Steven L. Shrader ; Robert A. Rust, Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface.
  43. Phillip M. Jones ; Robert Allan Lester, System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops.
  44. Thornton,Barry, System of co-located computers in a framework including removable function modules for adding modular functionality.
  45. Christensen Steven G. (Minneapolis MN), TDM digital matrix intercom system.
  46. Pettey,Christopher J., Work queue to TCP/IP translation.

이 특허를 인용한 특허 (9)

  1. Trisno, Tjandra; Sprague, Edward E.; Young, Scott A., Application of hardware-based mailboxes in network transceivers and distributed approach for predictable software-based protection switching.
  2. Yamada, Kazuo, Circuit design information generating equipment, function execution system, and memory medium storing program.
  3. Elboim, Yaron, Distributed interconnect bus apparatus.
  4. Lee, Jae-bok; Lee, Ki-cheol; Song, Yong Ho; Jeong, Jaehyeong, Interface system and method of controlling thereof.
  5. Frey, Bradly George; Thurber, Steven Mark; Wottreng, Andrew Henry, Method and apparatus for providing accelerator support in a bus protocol.
  6. Huang, Wei-Shun; Chou, Teh-Chern, Method for transmitting data between two computer systems.
  7. Cha, Hyun Seok; Jeon, Yong Tae; Noh, Ki Chul; Jung, Ki Jo; Jagadish, Chandrashekar Tandavapura; Komuravelli, Vamshi Krishna, Peripheral component interconnect (PCI) device and system including the PCI.
  8. Biran, Giora; Granovsky, Ilya; Perlin, Elchanan, System and method for a credit based flow device that utilizes PCI express packets having modified headers wherein ID fields includes non-ID data.
  9. Tamir, Tal; Rettig, Daniel, Wireless peripheral interconnect bus.
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