초록 ▼

An integrated circuit (1) has an array of single photon avalanche diodes (SPADS), a plurality of read-out circuits, each SPADS being coupled to one read-out circuit, wherein at least some of the read-out circuits comprise time-to-digital converters (TDC) and/or a digital asynchronous counter. The pl

An integrated circuit (1) has an array of single photon avalanche diodes (SPADS), a plurality of read-out circuits, each SPADS being coupled to one read-out circuit, wherein at least some of the read-out circuits comprise time-to-digital converters (TDC) and/or a digital asynchronous counter. The plurality of SPADS are coupled to one single read-out circuit. The read-out circuit may have a transformer for decoupling the SPAD from other parts of the read-out circuit.

대표청구항 ▼

The invention claimed is: 1. An integrated circuit comprising: an array of single photon avalanche diodes (SPADs), each SPAD having an output for delivering an electrical pulse each time a photon is received; a plurality of read-out circuits for processing said pulses, each SPAD output being couple

The invention claimed is: 1. An integrated circuit comprising: an array of single photon avalanche diodes (SPADs), each SPAD having an output for delivering an electrical pulse each time a photon is received; a plurality of read-out circuits for processing said pulses, each SPAD output being coupled to one of said read-out circuits, wherein a plurality of said SPAD outputs are coupled to one of said read-out circuits, and wherein said read-out circuits allow identification of the coupled SPAD that delivers said electrical pulse. 2. The integrated circuit of claim 1, wherein at least some of the read-out circuits comprise a time-to-digital converter (TDC) and/or a digital asynchronous counter. 3. The circuit of claim 2, wherein said TDCs are located on the circuit outside of said SPAD array. 4. The integrated circuit of claim 2, said array of single photon avalanche diodes and said read-out circuits being located on a single monolithic chip. 5. The circuit of claim 4, wherein said array comprises a plurality of rows of SPADs and a plurality columns of SPADs, wherein several SPADS in a column or row are coupled to the same read-out circuit. 6. The circuit of claim 4, wherein said SPADs are CMOS-implemented and operated in the Geiger mode. 7. The circuit of claim 6, wherein each SPAD is associated with a quenching/recharging transistor, with a CMOS circuit for converting the output of the SPAD into a digital signal, and with addressing transistors. 8. The circuit of claim 7, further comprising addressing lines for addressing different SPADs coupled to the same read-out circuit at different times. 9. The circuit of claim 7, further comprising on-chip buffers for temporarily storing value read by different SPADs. 10. The circuit of claim 9, comprising an external interface for reading value from said buffers. 11. The circuit of claim 9, wherein all SPADs in a column are coupled to a single read-out circuit, wherein a signal is immediately transferred to said read-out circuit when a photon has been detected by any SPAD in said column. 12. The circuit of claim 1, wherein said SPADs are read in a non sequential way. 13. The circuit of claim 12, wherein a signal is transferred to said read-out circuit immediately when a photon has been detected by any SPAD. 14. The circuit of claim 1, further comprising integrated transformers, one coil of each transformer being connected in series with one corresponding SPAD. 15. The circuit of claim 14, wherein said transformer is implemented by using resistive layers. 16. A monolithic integrated circuit comprising: an array of pixels, each pixel comprising a CMOS implemented single photon avalanche diodes (SPADs), an associated quenching device, a comparator for converting the output of the SPAD into a digital signal, and addressing transistors at the pixel level, a plurality of read-out circuits for determining the time of arrival of the pulses delivered by the SPADs and/or the number of pulses delivered by the SPADs, wherein several pixels are coupled to the same read-out circuit, and wherein said read-out circuits allow identification of the coupled pixel that delivers said pulse. 17. An imager comprising: an array of single photon avalanche diodes (SPADs), at least one time-to-digital converter (TDC), a plurality of SPADs being connected to a common TDC, wherein said TDC access the connected SPAD in a non sequential order depending on the order of arrival of the photons on the different SPADs wherein the SPAD that detects the photon is identified. 18. A method for capturing an image of a scene with an imager comprising an array of single photon avalanche diode (SPADs), wherein a digital signal is immediately transferred to a read-out circuit shared by several SPADs when a photon has been detected by any SPAD connected to said read-out circuit, wherein the SPAD that delivers said digital signal is identified. 19. The method of claim 18, wherein said digital signal indicates the SPAD which has detected said photon.