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A process for fabricating a thin film transistor including: (a) depositing a semiconductor layer; and (b) depositing a multilayer gate dielectric prior to or subsequent to the depositing the semiconductor layer, wherein the multilayer dielectric comprises: (i) a first layer comprising a first materi

A process for fabricating a thin film transistor including: (a) depositing a semiconductor layer; and (b) depositing a multilayer gate dielectric prior to or subsequent to the depositing the semiconductor layer, wherein the multilayer dielectric comprises: (i) a first layer comprising a first material selected from the group consisting of an optionally substituted silsesquioxane, an optionally substituted silsesquioxane-metal oxide hybrid composition, an optionally substituted siloxane-metal oxide hybrid composition, and a mixture thereof, and (ii) a second layer in contact with the first layer, wherein the second layer comprises a second material, wherein the first layer is closer to the semiconductor layer than the second layer.

대표청구항 ▼

The invention claimed is: 1. A process for fabricating a thin film transistor comprising: (a) depositing a semiconductor layer; and (b) depositing a multilayer gate dielectric prior to or subsequent to the depositing the semiconductor layer, wherein the multilayer dielectric comprises: (i) a first

The invention claimed is: 1. A process for fabricating a thin film transistor comprising: (a) depositing a semiconductor layer; and (b) depositing a multilayer gate dielectric prior to or subsequent to the depositing the semiconductor layer, wherein the multilayer dielectric comprises: (i) a first layer comprising a first material selected from the group consisting of an organosilsesquioxane-metal oxide hybrid composition, an organosiloxane-metal oxide hybrid composition, and a mixture thereof, and (ii) a second layer in contact with the first layer, wherein the second layer comprises a second material, wherein the first layer is closer to the semiconductor layer than the second layer wherein the first layer contacts the semiconductor layer wherein the first layer is subjected to a curing temperature ranging from about 140 to about 200 degrees C. 2. The process of claim 1, wherein the depositing the semiconductor layer is accomplished by liquid deposition. 3. The process of claim 1, wherein the depositing the multilayer gate dielectric is accomplished by liquid deposition. 4. The process of claim 1, wherein the depositing the semiconductor layer and the depositing the multilayer gate dielectric are both accomplished by liquid deposition. 5. The process of claim 1, wherein the second layer comprises an inorganic compound selected from the group consisting of silicon oxide, aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, zirconium oxide, lanthanum oxide, strontiates, tantalates, titanates, zirconates, silicon nitride, zinc selenide, zinc sulfide, and a mixture thereof. 6. The process of claim 1, wherein the second material is a non-crosslinked polymer comprising polymerized one or more monomers, wherein the one or more monomers includes an optionally substituted vinyl arylalcohol. 7. The process of claim 1, wherein the second material is a radiation-induced crosslinked polymer comprising polymerized one or more monomers, wherein the one or more monomers includes an optionally substituted vinyl arylalcohol. 8. The process of claim 1, wherein the second material is an optionally crosslinked copolymer of an optionally substituted vinyl arylalcohol and an acrylate. 9. The process of claim 1, wherein the second material is an optionally crosslinked copolymer of a vinylphenol and a methyl methacrylate. 10. The process of claim 1, wherein the second material is an optionally crosslinked poly(vinyl arylalcohol). 11. The process of claim 1, further comprising employing a plastic substrate.