$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of producing thin films 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 UP-0294843 (2005-12-05)
등록번호 US-7563715 (2009-07-29)
발명자 / 주소
  • Haukka, Suvi
  • Huotari, Hannu
출원인 / 주소
  • ASM International N.V.
대리인 / 주소
    Knobbe Martens Olson & Bear LLP
인용정보 피인용 횟수 : 36  인용 특허 : 93

초록

A process for producing metal nitride thin films comprising doping the metal nitride thin films by atomic layer deposition (ALD) with silicon or boron or a combination thereof. The work function of metal nitride thin films, which are used in metal electrode applications, can efficiently be tuned.

대표청구항

We claim: 1. A process for producing a boron or silicon doped metal nitride thin film on a substrate in a reaction chamber by atomic layer deposition, the process comprising at least one ALD cycle in which the following steps are performed in order: providing a first vapor phase reactant pulse comp

이 특허에 인용된 특허 (93)

  1. Shekhar Pramanick ; John A. Iacoponi, Alloy barrier layers for semiconductors.
  2. Vaartstra, Brian A., Aluminum-containing material and atomic layer deposition methods.
  3. Conger Darrell R. (Portland OR) Posa John G. (Lake Oswego OR) Wickenden Dennis K. (Lake Oswego OR), Apparatus for depositing material on a substrate.
  4. Li, Wei-Min, Atomic layer deposition methods for forming a multi-layer adhesion-barrier layer for integrated circuits.
  5. Zheng, Lingyi A.; Ping, Er-Xuan; Breiner, Lyle; Doan, Trung T., Atomic layer deposition of capacitor dielectric.
  6. Visokay, Mark Robert; Rotondaro, Antonio Luis Pacheco; Colombo, Luigi, Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing.
  7. Skarp Jarmo I. (Helsinki FIX), Combination film, in particular for thin film electroluminescent structures.
  8. Bai Gang ; Liang Chunlin, Complementary metal gates and a process for implementation.
  9. Raaijmakers, Ivo; Haukka, Suvi P.; Granneman, Ernst H. A., Conformal thin films over textured capacitor electrodes.
  10. Ding Peijun ; Chiang Tony ; Hashim Imran ; Sun Bingxi ; Chin Barry, Copper alloy seed layer for copper metallization in an integrated circuit.
  11. Bhattacharyya, Arup, Decoupling capacitor for high frequency noise immunity.
  12. Elers, Kai-Erik; Haukka, Suvi P.; Saanila, Ville Antero; Kaipio, Sari Johanna; Soininen, Pekka Juha, Deposition of transition metal carbides.
  13. Kai-Erik Elers FI; Suvi P. Haukka FI; Ville Antero Saanila FI; Sari Johanna Kaipio FI; Pekka Juha Soininen FI, Deposition of transition metal carbides.
  14. Takasu Katsuji,JPX ; Tsuda Hisanori,JPX ; Sano Masafumi,JPX ; Hirai Yutaka,JPX, Device for forming deposited film.
  15. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.
  16. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  17. Lopatin Sergey D. ; Nogami Takeshi, Graded compound seed layers for semiconductors.
  18. Sergey D. Lopatin ; Takeshi Nogami, Graded compound seed layers for semiconductors.
  19. Werkhoven, Christiaan J.; Raaijmakers, Ivo; Haukka, Suvi P., Graded thin films.
  20. Werkhoven, Christiaan J.; Raaijmakers, Ivo; Haukka, Suvi P., Graded thin films.
  21. Buchanan, Douglas A.; Callegari, Alessandro C.; Gribelyuk, Michael A.; Jamison, Paul C.; Neumayer, Deborah Ann, High mobility FETS using A1203 as a gate oxide.
  22. Fu, Tzy-Tzan; Lin, Kuan-Ting; Chou, Chao-Sheng, Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4.
  23. Chau Robert S. (Beaverton OR) Fraser David B. (Danville CA) Cadien Kenneth C. (Portland OR) Raghavan Gopal (Mountain View CA) Yau Leopoldo D. (Portland OR), MOS transistor having a composite gate electrode and method of fabrication.
  24. Yu Bin, MOS transistor with dual metal gate structure.
  25. Kirlin Peter S. (Bethel CT) Brown Duncan W. (Wilton CT) Gardiner Robin A. (Bethel CT), Metal complex source reagents for MOCVD.
  26. Elers,Kai; Li,Wei Min, Metal nitride deposition by ALD with reduction pulse.
  27. Watanabe Toru,JPX ; Okumura Katsuya,JPX ; Hieda Katsuhiko,JPX, Metallization structure and method for a semiconductor device.
  28. Jiang Tongbi ; Li Li, Method and apparatus for electroless plating a contact pad.
  29. Tongbi Jiang ; Li Li, Method and apparatus for electroless plating a contact pad.
  30. Posa John G. (Lake Oswego OR), Method and apparatus for producing a constant flow, constant pressure chemical vapor deposition.
  31. Lindfors,Sven, Method and apparatus of growing a thin film onto a substrate.
  32. Suntola Tuomo,FIX ; Lindfors Sven,FIX ; Soininen Pekka,FIX, Method and equipment for growing thin films.
  33. Uzoh, Cyprian; Basol, Bulent M.; Talieh, Homayoun, Method and structure for thru-mask contact electrodeposition.
  34. Nair Kumaran M. (East Amherst NY), Method for activating metal particles.
  35. Satta, Alessandra; Maex, Karen; Elers, Kai-Erik; Saanila, Ville Antero; Soininen, Pekka Juha; Haukka, Suvi P., Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
  36. Kelly Michael A. (121 Erica Way Portola Valley CA 94028), Method for chemical vapor deposition under a single reactor vessel divided into separate reaction chambers each with its.
  37. Ramdani, Jamal; Droopad, Ravindranath; Yu, Zhiyi, Method for fabricating a semiconductor structure including a metal oxide interface with silicon.
  38. Ueda Tohru,JPX ; Nakamura Kenta,JPX ; Fukushima Yasumori,JPX, Method for fabricating semiconductor nanocrystal and semiconductor memory device using the semiconductor nanocrystal.
  39. Park, Dae-Gyu; Jang, Se-Aug; Lee, Jeong-Youb; Cho, Hung-Jae; Kim, Jung-Ho, Method for forming aluminum oxide as a gate dielectric.
  40. Kang Sang-bom,KRX ; Chae Yun-sook,KRX ; Park Chang-soo,KRX ; Lee Sang-in,KRX, Method for forming metal layer using atomic layer deposition.
  41. Leskel채,Markku; Ritala,Mikko; Hatanp채채,Timo; H채nninen,Timo; Vehkam채ki,Marko, Method for growing oxide thin films containing barium and strontium.
  42. Liang Chunlin ; Bai Gang, Method for making a complementary metal gate electrode technology.
  43. Liang Chunlin ; Bai Gang, Method for making a complementary metal gate electrode technology.
  44. Suntola Tuomo (Riihikallio 02610 Espoo 61 SF) Antson Jorma (Urheilutie 22 ; 01350 Vantaa 35 SF), Method for producing compound thin films.
  45. Lasbmore, David S.; Dariel, Moshe P., Method for the production of predetermined concentration graded alloys.
  46. Meikle Scott G., Method of chemical mechanical polishing for dielectric layers.
  47. Meikle Scott (Boise ID) Ward Valerie (Boise ID), Method of chimical mechanical polishing for dielectric layers.
  48. Sergey D. Lopatin ; Carl Galewski ; Takeshi T. N. Nogami JP, Method of copper interconnect formation using atomic layer copper deposition.
  49. Haukka, Suvi; Huotari, Hannu, Method of depositing barrier layer for metal gates.
  50. Nishikawa Toru,JPX ; Satoh Ryohei,JPX ; Hara Masahide,JPX ; Hayashida Tetsuya,JPX ; Shirai Mitugu,JPX ; Yamada Osamu,JPX ; Takehara Hiroko,JPX ; Iwata Yasuhiro,JPX ; Tamura Mitsunori,JPX ; Ijuin Masa, Method of fabricating an electronic circuit device.
  51. Schinella, Richard, Method of forming SiGe gate electrode.
  52. Ma, Yanjun; Ono, Yoshi, Method of forming a multilayer dielectric stack.
  53. Huotari,Hannu; Haukka,Suvi; Tuominen,Marko, Method of forming an electrode with adjusted work function.
  54. Wilk Glen D. ; Summerfelt Scott R., Method of forming dual metal gate structures or CMOS devices.
  55. Werkhoven, Christiaan J.; Raaijmakers, Ivo; Haukka, Suvi P., Method of forming graded thin films using alternating pulses of vapor phase reactants.
  56. Chau Robert S. ; Fraser David B. ; Cadien Kenneth C. ; Raghavan Gopal ; Yau Leopoldo D., Method of frabricating a MOS transistor having a composite gate electrode.
  57. Pekka J. Soininen FI; Kai-Erik Elers FI; Suvi Haukka FI, Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH.
  58. Hirota Toshiyuki (Tokyo JPX) Honma Ichirou (Tokyo JPX) Watanabe Hirohito (Tokyo JPX) Zenke Masanobu (Tokyo JPX), Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode.
  59. Cha, Tae Ho; Jang, Se Aug; Kim, Tae Kyun; Park, Dea Gyu; Yeo, In Seok; Park, Jin Won, Method of manufacturing a transistor in a semiconductor device.
  60. Park, Dae Gyu; Cha, Tae Ho; Jang, Se Aug; Cho, Heung Jae; Kim, Tae Kyun; Lim, Kwan Yong; Yeo, In Seok; Park, Jin Won, Method of manufacturing semiconductor devices with titanium aluminum nitride work function.
  61. Wenhe Lin SG; Mei-Sheng Zhou SG; Kin Leong Pey SG; Simon Chooi SG, Methods to form dual metal gates by incorporating metals and their conductive oxides.
  62. Ajit P. Paranjpe ; Mehrdad M. Moslehi ; Boris Relja ; Randhir S. Bubber ; Lino A. Velo ; Thomas R. Omstead ; David R. Campbell, Sr. ; David M. Leet ; Sanjay Gopinath, Microelectronic interconnect material with adhesion promotion layer and fabrication method.
  63. Yanjun Ma ; Yoshi Ono, Multilayer dielectric stack and method.
  64. Senzaki, Yoshihide, Multilayer high κ dielectric films.
  65. Chun-Ching Tsan TW; Hung-Ju Chien TW; Chun-Chang Chen TW; Ying-Lang Wang TW, PE-silane oxide particle performance improvement.
  66. Obeng Yaw Samuel ; Obeng Jennifer S., Passivated copper surfaces.
  67. Foster Robert F. (Phoenix AZ) Hillman Joseph T. (Scottsdale AZ) Arora Rikhit (Mesa AZ), Plasma enhanced chemical vapor deposition of titanium nitride using ammonia.
  68. Nishizawa Junichi (6-16 ; Komegafukuro 1-chome Sandai-shi ; Miyagi-ken JPX) Abe Hitoshi (1-3 ; Otamayashita Sendai JPX) Suzuki Soubei (1-3 ; Otamayashita Sendai-shi ; Miyagi-ken JPX), Process for forming a thin film of silicon.
  69. Ando Kazuhiro (Ibaraki JPX) Kawakami Takamasa (Ibaraki JPX) Shouji Yasuhiro (Ibaraki JPX) Tanaka Yasuo (Tokyo JPX) Kanaoka Takeo (Tokyo JPX) Sayama Norio (Tokyo JPX), Process for producing copper clad laminate.
  70. Soininen, Pekka Juha; Elers, Kai-Erik, Process for producing integrated circuits including reduction using gaseous organic compounds.
  71. Aaltonen, Titta; Alén, Petra; Ritala, Mikko; Leskelä, Markku, Process for producing metal thin films by ALD.
  72. Ngo Minh Van ; Morales Guarionex ; Nogami Takeshi, Process for reducing copper oxide during integrated circuit fabrication.
  73. Stephen N. Vaughn ; Peter G. Ham ; Keith H. Kuechler, Process to control conversion of C4+ and heavier stream to lighter products in oxygenate conversion reactions.
  74. Raaijmakers, Ivo; Soininen, Pekka T.; Granneman, Ernst H. A.; Haukka, Suvi P., Protective layers prior to alternating layer deposition.
  75. Sneh Ofer, Radical-assisted sequential CVD.
  76. Verghese,Mohith; Shero,Eric J., Reactor surface passivation through chemical deactivation.
  77. Paranjpe Ajit P. ; Moslehi Mehrdad M. ; Bubber Randhir S. ; Velo Lino A., Semiconductor chip interconnect barrier material and fabrication method.
  78. Ngai, Tat; Nguyen, Bich-Yen; Kaushik, Vidya S.; Schaeffer, Jamie K., Semiconductor device and a method therefor.
  79. Chabal, Yves Jean; Green, Martin Laurence; Wilk, Glen David, Semiconductor device having a high-K gate dielectric and method of manufacture thereof.
  80. Matsuo Mie,JPX ; Okano Haruo,JPX ; Hayasaka Nobuo,JPX ; Suguro Kyoichi,JPX ; Miyajima Hideshi,JPX ; Wada Jun-ichi,JPX, Semiconductor device having a metal film formed in a groove in an insulating film.
  81. Isik C. Kizilyalli ; Ranbir Singh ; Lori Stirling, Semiconductor device having a metal gate with a work function compatible with a semiconductor device.
  82. Masayuki Shimizu JP, Semiconductor device having fluorined insulating film and reduced fluorine at interconnection interfaces and method of manufacturing the same.
  83. Gardner Mark I. ; Fulford H. Jim ; May Charles E. ; Hause Fred ; Kwong Dim-Lee, Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof.
  84. Arthur Sherman, Sequential chemical vapor deposition.
  85. Sherman Arthur, Sequential chemical vapor deposition.
  86. Ikari, Atsushi; Hasebe, Masami; Nakai, Katsuhiko; Sakamoto, Hikaru; Ohashi, Wataru; Hoshino, Taizo; Iwasaki, Toshio, Silicon semiconductor wafer and method for producing the same.
  87. Pomarede, Christophe F.; Roberts, Jeff; Shero, Eric J., Surface preparation prior to deposition.
  88. Mori Yoshiaki,JPX ; Miyakawa Takuya,JPX ; Takahashi Katsuhiro,JPX ; Miyashita Takeshi,JPX ; Katagami Satoru,JPX, Surface treatment method.
  89. Nguyen Tue ; Charneski Lawrence J. ; Evans David R. ; Hsu Sheng Teng, System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides.
  90. Hegde, Rama I.; Mogab, Joe; Tobin, Philip J.; Tseng, Hsing H.; Liu, Chun-Li; Borucki, Leonard J.; Merchant, Tushar P.; Hobbs, Christopher C.; Gilmer, David C., Transistor with layered high-K gate dielectric and method therefor.
  91. Akatsu Hiroyuki ; Dokumaci Omer H. ; Hegde Suryanarayan G. ; Li Yujun ; Rengarajan Rajesh,DEX ; Ronsheim Paul A., Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer.
  92. Jun-Fei Zheng ; Brian Doyle ; Gang Bai ; Chunlin Liang, Work function tuning for MOSFET gate electrodes.
  93. Izumi Hirohiko (Sagamihara JPX), .

이 특허를 인용한 특허 (36)

  1. Ootsuka, Fumio, 3D stacked multilayer semiconductor memory using doped select transistor channel.
  2. Oosterlaken, Theodorus; de Ridder, Chris; Jdira, Lucian, Apparatus and method for manufacturing a semiconductor device.
  3. den Hartog Besselink, Edwin; Garssen, Adriaan; Dirkmaat, Marco, Cassette holder assembly for a substrate cassette and holding member for use in such assembly.
  4. Raisanen, Petri; Shero, Eric; Haukka, Suvi; Milligan, Robert Brennan; Givens, Michael Eugene, Deposition of metal borides.
  5. Zhu, Chiyu; Shrestha, Kiran; Haukka, Suvi, Deposition of metal borides.
  6. Milligan, Robert Brennan, Formation of boron-doped titanium metal films with high work function.
  7. Lin, Cheng-Tung; Chiu, Yung-Sheng; Wang, Hsiang-Yi; Yu, Chia-Lin; Yu, Chen-Hua, MOSFETs having stacked metal gate electrodes and method.
  8. Pore, Viljami, Method and apparatus for filling a gap.
  9. Pore, Viljami; Knaepen, Werner; Jongbloed, Bert; Pierreux, Dieter; Van Aerde, Steven R. A.; Haukka, Suvi; Fukuzawa, Atsuki; Fukuda, Hideaki, Method and apparatus for filling a gap.
  10. Pore, Viljami; Knaepen, Werner; Jongbloed, Bert; Pierreux, Dieter; Van Der Star, Gido; Suzuki, Toshiya, Method and apparatus for filling a gap.
  11. Cheng, Kangguo; Adam, Thomas N.; Khakifirooz, Ali; Reznicek, Alexander, Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts.
  12. Cheng, Kangguo; Doris, Bruce B.; Khakifirooz, Ali; Shahidi, Ghavam, Method and structure for forming on-chip high quality capacitors with ETSOI transistors.
  13. Cheng, Kangguo; Doris, Bruce B.; Khakifirooz, Ali; Shahidi, Ghavam, Method and structure for forming on-chip high quality capacitors with ETSOI transistors.
  14. Kang, DongSeok, Method for depositing thin film.
  15. Kato, Richika; Nakano, Ryu, Method for protecting layer by forming hydrocarbon-based extremely thin film.
  16. Zaitsu, Masaru; Kobayashi, Nobuyoshi; Kobayashi, Akiko; Hori, Masaru; Kondo, Hiroki; Tsutsumi, Takayoshi, Method of cyclic dry etching using etchant film.
  17. Horak, David Vaclav; Ponoth, Shom; Shobha, Hosadurga; Yang, Chih-Chao, Method of fabricating semiconductor capacitor.
  18. Knaepen, Werner; Maes, Jan Willem; Jongbloed, Bert; Kachel, Krzysztof Kamil; Pierreux, Dieter; De Roest, David Kurt, Method of forming a structure on a substrate.
  19. Lee, Choong Man; Yoo, Yong Min; Kim, Young Jae; Chun, Seung Ju; Kim, Sun Ja, Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method.
  20. Park, Sang Hee; Hwang, Chi Sun; Chu, Hye Yong; Lee, Jeong Ik, Method of manufacturing P-type ZnO semiconductor layer using atomic layer deposition and thin film transistor including the P-type ZnO semiconductor layer.
  21. Park, Sang Hee; Hwang, Chi Sun; Chu, Hye Yong; Lee, Jeong Ik, Method of manufacturing P-type ZnO semiconductor layer using atomic layer deposition and thin film transistor including the P-type ZnO semiconductor layer.
  22. Tak, Yong-suk; Kang, Min-jae; Lee, Ju-ri, Method of manufacturing integrated circuit device.
  23. Chun, Seung Ju; Yoo, Yong Min; Choi, Jong Wan; Kim, Young Jae; Kim, Sun Ja; Lim, Wan Gyu; Min, Yoon Ki; Lee, Hae Jin; Yoo, Tae Hee, Method of processing a substrate and a device manufactured by using the method.
  24. Kohen, David; Profijt, Harald Benjamin, Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures.
  25. Raisanen, Petri; Givens, Michael Eugene, Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures.
  26. Kim, Jong Su; Park, Hyung Sang; Yoo, Yong Min; Kwon, Hak Yong; Yoon, Tae Ho, Methods of forming an amorphous silicon thin film.
  27. Ando, Takashi; Dasgupta, Aritra; Kwon, Unoh; Polvino, Sean M., Multi-layer work function metal replacement gate.
  28. Ando, Takashi; Dasgupta, Aritra; Kwon, Unoh; Polvino, Sean M., Multi-layer work function metal replacement gate.
  29. Zhu, Chiyu; Asikainen, Timo; Milligan, Robert Brennan, NbMC layers.
  30. Margetis, Joe; Tolle, John; Bartlett, Gregory; Bhargava, Nupur, Process for forming a film on a substrate using multi-port injection assemblies.
  31. Alokozai, Fred; Milligan, Robert Brennan, Process gas management for an inductively-coupled plasma deposition reactor.
  32. Zhu, Chiyu, Selective film deposition method to form air gaps.
  33. Horak, David Vaclav; Ponoth, Shom; Shobha, Hosadurga; Yang, Chih-Chao, Semiconductor capacitor.
  34. Kim, Young Jae; Choi, Seung Woo; Yoo, Yong Min, Semiconductor device and manufacturing method thereof.
  35. Xie, Qi; de Roest, David; Woodruff, Jacob; Givens, Michael Eugene; Maes, Jan Willem; Blanquart, Timothee, Source/drain performance through conformal solid state doping.
  36. Jeong, Sang Jin; Han, Jeung Hoon; Choi, Young Seok; Park, Ju Hyuk, Susceptor for semiconductor substrate processing apparatus.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로