초록
▼
A semiconductor power device comprises a flange, a die having a gate, a source, and a drain. The source is electrically coupled to the flange. A drain matching circuit is located on the flange having an input, an output and a bias input, the input being coupled with the drain. The drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor ...
A semiconductor power device comprises a flange, a die having a gate, a source, and a drain. The source is electrically coupled to the flange. A drain matching circuit is located on the flange having an input, an output and a bias input, the input being coupled with the drain. The drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor. An input terminal is mechanically coupled to the flange and electrically coupled with the gate, an output terminal is mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit, and an input bias terminal is mechanically coupled to the flange and electrically coupled with the drain through the bias input.
대표
청구항
▼
What is claimed is: 1. A semiconductor power device comprising: a flange; a die having a gate, a source, and a drain, wherein the source is electrically coupled to the flange; a drain matching circuit located on the flange having an input, an output and a bias input, the input being coupled with the drain, wherein the drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and...
What is claimed is: 1. A semiconductor power device comprising: a flange; a die having a gate, a source, and a drain, wherein the source is electrically coupled to the flange; a drain matching circuit located on the flange having an input, an output and a bias input, the input being coupled with the drain, wherein the drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor; an input terminal being mechanically coupled to the flange and electrically coupled with the gate; an output terminal being mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit; and an input bias terminal being mechanically coupled to the flange and electrically coupled with the drain through the bias input. 2. The semiconductor power device as in claim 1, wherein the value of the second capacitor is large in comparison to the first capacitor and the distance between the first capacitor and the second capacitor is small, wherein a coupling bond wire creates a small inductance. 3. The semiconductor power device as in claim 1, further comprising: a gate matching circuit located on the flange having an input and an output, the output being coupled to the gate; and an input bias terminal being mechanically, coupled to the flange and electrically coupled with the gate through said gate matching circuit. 4. The semiconductor power device as in claim 1, wherein the die is a LDMOS transistor. 5. The semiconductor power device as in claim 3, wherein the gate matching network comprises two T networks and a shunt network. 6. The semiconductor power device as in claim 5, wherein the bias input terminal is coupled via a T network with the shunt network. 7. The semiconductor power device as in claim 5, wherein each T network comprises a first and second bond wire coupled in series and a capacitor coupled between the connection of the bond wires and source. 8. The semiconductor power device as in claim 3, further comprising an input blocking capacitor being electrically coupled between the input terminal and the gate. 9. The semiconductor power device as in claim 8, wherein the blocking capacitor is located on the proximal end of the input terminal. 10. The semiconductor power device as in claim 1, further comprising an output blocking capacitor being electrically coupled between the output terminal and the drain. 11. The semiconductor power device as in claim 10, wherein the blocking capacitor is located on the proximal end of the output terminal. 12. The semiconductor power device as in claim 3, wherein a plurality of dies, a plurality of gate matching circuits and a plurality of drain matching circuits is provided. 13. The semiconductor power device as in claim 1, wherein the input of the drain matching network is coupled with the output of the drain matching network through an inductor. 14. The semiconductor power device as in claim 13, wherein the inductor is formed by a bond wire. 15. The semiconductor power device as in claim 1, wherein the bias input of the drain matching network is coupled with the input bias terminal through an inductor. 16. The semiconductor power device as in claim 15, wherein the inductor is formed by a bond wire. 17. The semiconductor power device as in claim 2, wherein the first inductor has a value of about 200 pH, and the first capacitor has a value of about 200 pF, the second inductor has a value of about 100 pH, and the second inductor has a value of about 10 nF. 18. A broadband radio frequency (RF) signal amplifier, comprising: at least one transistor attached to a surface of a pedestal, the transistor having a RF input and a RF output, a bias input and a bias output; the pedestal comprising a support structure, reference ground and heat sink for the transistor, RF input path electrically connected to the transistor input, an input matching network configured to couple the input signal to the transistor input at an input impedance, an input direct current (dc) bias network configured to bias the transistor input to an input operating point, an RF output path electrically connected to the transistor output, and an output matching network configured to couple the respective component output signal to the transistor output at an output impedance, and an output dc bias networks configured to bias the transistor output to an output operating point, wherein the output dc bias network comprises an inductor coupled in series with a first capacitor between the drain and reference ground and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor. 19. The amplifier of claim 18, wherein the value of the second capacitor is large in comparison to the first capacitor and the distance between the first capacitor and the second capacitor is small, wherein a coupling bond wire creates a small inductance. 20. The amplifier of claim 18, wherein a plurality of transistors is provided on the pedestal and wherein the input path includes a splitter configured to split a RF input signal into a plurality of component input signals. 21. The amplifier of claim 20, wherein the output path includes a signal merger configured to combine component output signals received at the transistor outputs into a RF output signal. 22. The amplifier of claim 18, wherein the inductors are formed by bond wires. 23. The amplifier of claim 18, wherein the input matching network comprises a transmission line implemented in a printed circuit board and electrically connecting the component input signals to respective transistor inputs, the transmission lines having lengths, approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal. 24. The amplifier of claim 18, wherein the output matching network comprises transmission lines implemented in a printed circuit board and electrically connecting component output signals to the combiner, the transmission lines having lengths approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal. 25. The amplifier of claim 21, wherein the signal splitter and signal merger are passive elements. 26. The amplifier of claim 18, wherein the input impedance is relatively high, and the input operating point is relatively low. 27. The amplifier of claim 21, further comprising a first plurality of conductors electrically connecting respective input, path transmission lines to respective transistor inputs, and a second plurality of conductors electrically connecting respective output path transmission lines to respective transistor outputs. 28. A semiconductor power device comprising: a flange; a die having a gate, a source, and a drain, wherein the source is electrically coupled to the flange; a gate matching circuit located on the flange having an input and an output, the output being coupled to the gate; an input bias terminal being mechanically, coupled to the flange and electrically coupled with the gate through said gate matching circuit; a drain matching circuit located on the flange having an input, an output and a bias input, the input being coupled with the drain, wherein the drain matching circuit comprises an inductor coupled in series with a first capacitor between the drain and flange and a second capacitor arranged next to the first capacitor, wherein the second capacitor is coupled with the bias input and in parallel with the first capacitor through a second inductor, and wherein the value of the second capacitor is large in comparison to the first capacitor and the distance between the first capacitor and the second capacitor is small, wherein a coupling bond wire creates a small inductance; an input terminal being mechanically coupled to the flange and electrically coupled with the gate; an output terminal being mechanically coupled to the flange and electrically coupled with the output of the drain matching circuit; and an input bias terminal being mechanically coupled to the flange and electrically coupled with the drain through the bias input. 29. The semiconductor power device as in claim 28, wherein the gate matching network comprises two T network and a shunt network. 30. The semiconductor power device as in claim 29, wherein the bias input terminal and the is coupled with the respective shunt network. 31. The semiconductor power device as in claim 29, wherein each T network comprises a first and second bond wire coupled in series and a capacitor coupled between the connection of the bond wires and source. 32. The semiconductor power device as in claim 28, further comprising an input blocking capacitor being electrically coupled between the input terminal and the gate. 33. The semiconductor power device as in claim 32, wherein the blocking capacitor is located on the proximal end of the input terminal. 34. The semiconductor power device as in claim 28, further comprising an output blocking capacitor being electrically coupled between the output terminal and the drain. 35. The semiconductor power device as in claim 34, wherein the blocking capacitor is located on the proximal end of the output terminal. 36. The semiconductor power device as in claim 28, wherein a plurality of dies, a plurality of gate matching circuits and a plurality of drain matching circuits is provided. 37. The semiconductor power device as in claim 28, wherein the input of the drain matching network is coupled with the output of the drain matching network through an inductor. 38. The semiconductor power device as in claim 37, wherein the inductor is formed by a bond wire. 39. The semiconductor power device as in claim 28, wherein the bias input of the drain matching network is coupled with the input bias terminal through an inductor. 40. The semiconductor power device as in claim 39, wherein the inductor is formed by a bond wire. 41. The semiconductor power device as in claim 28, wherein the first inductor has a value of about 200 pH, and the first capacitor has a value of about 200 pF, the second inductor has a value of about 100 pH, and the second inductor has a value of about 10 nF.
