초록 ▼

A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p-or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and

A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p-or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.

대표청구항 ▼

Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is: 1. A method of fabricating a silicon-on-insulator substrate comprising: a first ion implanting step to implant p-type or n-type dopants into a Si-containing substrate to a depth rangin

Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is: 1. A method of fabricating a silicon-on-insulator substrate comprising: a first ion implanting step to implant p-type or n-type dopants into a Si-containing substrate to a depth ranging from 250 nm to 1500 nm from a top surface of the Si-containing substrate; a second ion implanting step following the first ion implanting step to implant at least one ion selected from the group consisting of Si, Ge, Ne, Bi, Sn and Xe, wherein the at least one ion may be implanted to below, above or within the depth at which the p-type or n-type dopants are present in the Si-containing substrate; annealing the n-type or p-type dopants following the second ion implanting step to provide an activated n-type or p-type dopant region in the Si-containing substrate; performing an electrolytic anodization process comprising immersing the Si-containing substrate into an HF-containing solution and applying a current density ranging from 0.05 milliAmps/cm2 to 50 milliAmps/cm2 to the Si-containing substrate to produce a porous Si region having a porosity of 0.01% or greater at a depth greater than 50 nm from the upper surface of the Si-containing substrate, wherein the electrolytic anodization process converts the activated n-type or p-type dopant region into the porous Si region; and thermal oxidizing at a temperature ranging from 650° C. to 1350° C. to convert at least a portion of the porous Si region into a buried oxide region, wherein a portion of the Si-containing substrate overlying the buried oxide region and a remaining portion of the porous Si region coalesces to provide a Si-containing overlayer. 2. The method of claim 1 wherein the first ion implanting step of the p-type or n-type dopants is ion implanting the p-type dopant in which the p-type dopant is selected from the group consisting of Ga, Al, B and BF2. 3. The method of claim 2 wherein the p-type dopant is B, said B is implanted at an energy of from about 100 keV to about 500 keV and a dose of about 5E15 atoms/cm2 to about 5E16 atom/cm2. 4. The method of claim 2 wherein the p-type dopant is BF2, said BF2 is implanted at an energy of from about 500 keV to about 2500 keV and a dose of about 5E15 atoms/cm2 to about 5E16 atom/cm2. 5. The method of claim 1 wherein the annealing comprises a furnace anneal, a rapid thermal anneal, or a spike anneal. 6. The method of claim 5 wherein the annealing is a furnace anneal step, said furnace anneal step is carried out at a temperature of about 600° C. or greater for a time period of about 15 minutes or greater in the presence of an inert gas atmosphere, an oxidizing ambient or a mixture thereof. 7. The method of claim 5 wherein the annealing is a rapid thermal anneal (RTA) step, said RTA step is carried out at a temperature of about 800° C. or greater for a time period of about 5 minutes or less in the presence of an inert gas atmosphere, an oxidizing ambient or a mixture thereof. 8. The method of claim 5 wherein the annealing is a spike annealing step, said spike annealing step is performed at a temperature of about 900° C. or greater for a time period of about 1 second or less in the presence of an inert gas atmosphere, an oxidizing ambient or a mixture thereof. 9. The method of claim 1 further comprising forming a cap layer atop the Si-containing substrate after said electrolytic anodization process, but prior to said oxidizing. 10. The method of claim 9 wherein the cap layer comprises a Si-containing material. 11. The method of claim 1 wherein the thermal oxidizing is performed in an oxygen-containing ambient. 12. The method of claim 11 wherein the oxygen-containing ambient further comprises an inert gas. 13. The method of claim 12 wherein the oxygen-containing ambient is selected from the group consisting of O2, NO, N2O, ozone, and air. 14. The method of claim 1 wherein the thermal oxidizing is performed at a temperature of from about 1200° C. to about 1325° C. 15. The method of claim 1 wherein the thermal oxidizing forms a surface oxide atop the Si-containing over-layer. 16. The method of claim 1 wherein the buried oxide region is uniform. 17. The method of claim 1 wherein the buried oxide region comprises discrete islands of thermal oxide. 18. The method of claim 1 further comprising a pre-oxidization step prior to said thermal oxidizing, said pre-oxidization step includes oxidation in a wet oxygen ambient. 19. The method of claim 18 wherein said pre-oxidization step is performed at a temperature from about 600° C. to about 1200° C. 20. The method of claim 1 further comprising a post oxidation step, said post oxidation step comprising a thermal anneal in a hydrogen ambient. 21. The method of claim 20 wherein the post oxidization step is performed at a temperature from about 900° C. to about 1200° C. 22. The method of claim 1 wherein said at least one ion of said second ion implanting step is Si and said second ion implanting step is performed using a Si dose from about 1E15 to about 1E16 atoms/cm2 and an implant energy from about 200 to about 500 keV. 23. The method of claim 1 further comprising patterning the Si-containing substrate prior to the ion implanting of the p-type or n-type dopants into the Si-containing substrate.