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A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and

A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.

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The invention claimed is: 1. A thin-film transistor backplane circuit comprising: a substrate; a dielectric layer formed on the upper surface of the substrate; a plurality of thin-film transistors formed on the dielectric layer, each of the thin-film transistors including a drain contact structure,

The invention claimed is: 1. A thin-film transistor backplane circuit comprising: a substrate; a dielectric layer formed on the upper surface of the substrate; a plurality of thin-film transistors formed on the dielectric layer, each of the thin-film transistors including a drain contact structure, a source contact structure, and an organic semiconductor region disposed between the source and drain contact structures; a plurality of readout amplifiers disposed adjacent to said plurality of thin-film transistors; and a plurality of address lines formed on the dielectric layer, each address line connecting the drain contact structures of a column of said plurality of thin-film transistors with an associated readout amplifier of said plurality of readout amplifiers, wherein each of the plurality of address lines extending from said column of said plurality of thin-film transistors to said associated read-out amplifier and the source and drain contact structures of each of the plurality of transistors respectively comprise a multi-layer structure including a base portion and a contact layer, wherein the base portion comprises a first material and includes a lower surface, an upper surface extending parallel to the lower surface, and opposing side surfaces extending between the lower and upper surfaces, and wherein the contact layer comprises a second material that is different from the first material, and the contact layer includes: a first portion that is disposed between the base portion and a side surface of the organic semiconductor region, and extends from the dielectric layer to the upper surface of the base portion, and a second portion formed opposite to at least one of the upper surface, the lower surface of the base portion, and at least one of the opposing side surfaces, wherein the second portion extends along said each of the plurality of address lines to an associated one of said source and drain contact structures, wherein the first material of the base portion consists essentially of one of aluminum and copper, and wherein the second material of the contact layer comprises one of nickel, gold, palladium, platinum and a conductive polymer. 2. The backplane circuit according to claim 1, wherein each thin-film transistor defines a first interface region located between a first base portion of an associated drain contact structure and a first portion of an associated organic semiconductor region, and a second interface region located between a second base portion of an associated source contact structure and a second portion of said associated organic semiconductor region, wherein at least a portion of a first contact layer of the associated drain contact structure is located in the first interface region, and wherein at least a portion of a second contact layer of the associated source contact structure is located in the second interface region. 3. The backplane circuit according to claim 1, wherein the first material of the base portion has a first thickness, and wherein the second material of the contact layer has a second thickness, and wherein the first thickness is five times the second thickness. 4. The backplane circuit according to claim 3, wherein the first material comprises aluminum, and wherein the second material comprises one of poly(3,4-ethylenedioxythiophene) (PEDOT) and polyaniline (PANI). 5. The backplane circuit according to claim 3, wherein the first material comprises copper. 6. The backplane circuit according to claim 3, wherein the first material comprises aluminum, and wherein the contact layer comprises a first layer of nickel formed on the aluminum, and a second layer of gold formed on the nickel. 7. The backplane circuit according to claim 1, further comprising: a plurality of gate structures formed on an upper surface of the substrate; wherein the drain contact structure, the source contact structure, and the organic semiconductor region of each of the plurality of thin-film transistors are formed on an upper surface of the dielectric layer and arranged such that each gate structure is located under said organic semiconductor region. 8. The backplane circuit according to claim 1, wherein the second portion of the contact layer comprises first and second contact layers respectively disposed on the opposing side surfaces of the base portion. 9. The backplane circuit according to claim 1, wherein the second portion of the contact layer is disposed on the upper surface of the base portion. 10. The backplane circuit according to 1, wherein the second portion of the contact layer is disposed between the upper surface of the dielectric layer and the lower surface of the base portion. 11. A thin-film transistor backplane circuit comprising: a plurality of thin-film transistors, each of the thin-film transistors including a drain contact structure, a source contact structure, and an organic semiconductor region disposed between the source and drain contact structures; a plurality of readout amplifiers disposed adjacent to said plurality of thin-film transistors; and a plurality of address lines, each address line connecting the drain contact structures of a column of said plurality of thin-film transistors with an associated readout amplifiers of said plurality of readout amplifiers, wherein each of the plurality of address lines extending from said column of said plurality of thin-film transistors to said associated read-out amplifier and the source and drain contact structures of each of the plurality of transistors respectively comprise a multi-layer structure including a base portion and a contact layer, wherein the base portion consists essentially of one of aluminum and copper, includes a lower surface, an upper surface extending parallel to the lower surface, and a side surface extending between the lower and upper surfaces, and wherein the contact layer comprises one of nickel, gold, palladium, platinum and a conductive polymer, and includes: a first portion that is disposed between the base portion and a side surface of the organic semiconductor region, and extends from the lower surface of the base portion to the upper surface of the base portion, and a second portion formed opposite to at least one of the upper surface, the lower surface of the base portion, and the side surface of the base portion, wherein the second portion extends along said each of the plurality of address lines to an associated one of said source and drain contact structures, wherein the drain contact structure and the source contact structure are formed under a lower surface of the organic semiconductor region, and wherein the backplane circuit further comprises: a dielectric layer formed on an upper surface of the organic semiconductor region; and a plurality of gate structures formed on an upper surface of the dielectric layer. 12. A thin-film transistor backplane circuit comprising: a dielectric layer having an upper surface; a plurality of thin-film transistors, each of the thin-film transistors including a drain contact structure, a source contact structure, and an organic semiconductor region disposed between the source and drain contact structures; wherein the drain contact structure, the source contact structure, and the organic semiconductor region of each of the plurality of thin-film transistors are formed on the upper surface of the dielectric layer such that each of the contact structure, the source contact structure, and the organic semiconductor region contact the upper surface of the dielectric layer; a plurality of readout amplifiers disposed adjacent to said plurality of thin-film transistors; and a plurality of address lines, each address line connecting the drain contact structures of a column of said plurality of thin-film transistors, with an associated readout amplifier of said plurality of readout amplifiers, wherein each of the plurality of address lines extending from said column of said plurality of thin-film transistors to said associated read-out amplifier and the source and drain contact structures of each of the plurality of transistors respectively comprise a multi-layer structure including a base portion and a relatively thin contact layer, wherein the base portion is thicker than the contact layer, wherein each thin-film transistor defines a first interface region located between a first base portion of an associated drain contact structure and a first portion of an associated organic semiconductor region, and a second interface region located between a second base portion of an associated source contact structure and a second portion of said associated organic semiconductor region, wherein at least a first portion of a first contact layer of the associated drain contact structure is located in the first interface region such that the first base portion is entirely separated from the first portion of said associated organic semiconductor region by the first portion of the first contact layer, and wherein at least a first portion of a second contact layer of the associated source contact structure is located in the second interface region such that the second base portion is entirely separated from the second portion of said associated organic semiconductor region by the first portion of the second contact layer, wherein the base portion comprises a first material consisting essentially of one of aluminum and copper, and wherein the contact layer comprises a second material including one of nickel, gold, palladium, platinum and a conductive polymer. 13. The backplane circuit according to claim 12, wherein the first material comprises aluminum, and wherein the second material comprises one of poly(3,4-ethylenedioxythiophene) (PEDOT) and polyaniline (PANI). 14. The backplane circuit according to claim 12, wherein the first material comprises copper. 15. The backplane circuit according to claim 12, wherein the first material comprises aluminum, and wherein the contact layer comprises a first layer of nickel formed on the aluminum, and a second layer of gold formed on the nickel. 16. The backplane circuit according to claim 12, further comprising: a substrate; and a plurality of gate structures formed on an upper surface of the substrate, wherein the dielectric layer is formed on the upper surface of the substrate over the gate structures, and wherein the dielectric layer is formed on the upper surface of the substrate over the gate structures, and wherein the drain contact structure, the source contact structure, and the organic semiconductor region of each of the plurality of thin-film transistors are formed on the upper surface of the dielectric layer such that each gate structure is located under said organic semiconductor region. 17. The backplane circuit according to claim 16, wherein each of the first and second base portions comprises a lower surface disposed on the upper surface of the dielectric layer, and a side surface extending away from the lower surface adjacent to the organic semiconductor region, and an upper surface extending parallel to the lower surface and located at an upper end of the side surface. 18. The backplane circuit according to claim 17, wherein each of the first and second contact layers further comprises a second portion disposed on the upper surface of an associated one of the first and second base portions. 19. The backplane circuit according to claim 17, wherein each of the first and second contact layers comprises a second portion disposed between the upper surface of the dielectric layer and the lower surface of an associated one of the first and second base portions.