초록 ▼

Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performanc

Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the 'BER floor' that is sometimes problematic with conventional turbo decoders.

대표청구항 ▼

What is claimed: 1. An iterative decoder, comprising: an internal code decoder operable to perform iterative decoding of a data block; and an external code decoder capable of supplying a feedback signal to the internal decoder wherein the feedback signal is used to influence selective decisions dur

What is claimed: 1. An iterative decoder, comprising: an internal code decoder operable to perform iterative decoding of a data block; and an external code decoder capable of supplying a feedback signal to the internal decoder wherein the feedback signal is used to influence selective decisions during subsequent decoding iterations of the data block. 2. The iterative decoder of claim 1, wherein the internal code decoder comprises a binary convolutional code decoder. 3. The iterative decoder of claim 2, wherein the binary convolutional code decoder comprises a trellis coded modulation decoder. 4. The iterative decoder of claim 2, wherein the binary convolutional code decoder comprises a bit interleaved coded modulation decoder. 5. The iterative decoder of claim 1, wherein the internal code decoder comprises a turbo decoder. 6. The iterative decoder of claim 5, wherein the turbo decoder operates on a serial concatenated code. 7. The iterative decoder of claim 5, wherein the turbo decoder operates on a parallel concatenated code. 8. The iterative decoder of claim 5, wherein the turbo decoder operates on a hybrid serial/parallel concatenated code. 9. The iterative decoder of claim 5, wherein the turbo decoder operates on a turbo product code. 10. An iterative decoder method, comprising: performing iterative internal decoding of a data block; and feeding back external decoding information to influence selective decisions during subsequent internal decoding iterations of the data block. 11. An iterative decoder, comprising: means for performing iterative decoding of a data block; and means for supplying a feedback signal to the internal decoder wherein the feedback signal is used to influence selective decisions during subsequent decoding iterations of the data block. 12. The iterative decoder of claim 11, wherein the means for performing iterative decoding comprises a means for performing binary convolutional code decoding. 13. The iterative decoder of claim 12, wherein the means for performing binary convolutional code decoding comprises means for performing trellis coded modulation decoding. 14. The iterative decoder of claim 12, wherein the means for performing binary convolutional code decoding comprises means for performing bit interleaved coded modulation decoding. 15. The iterative decoder of claim 11, wherein the means for performing iterative decoding comprises means for performing turbo decoding. 16. The iterative decoder of claim 15, wherein the means for performing turbo decoding operates on a serial concatenated code. 17. The iterative decoder of claim 15, wherein the means for performing turbo decoding operates on a parallel concatenated code. 18. The iterative decoder of claim 15, wherein the means for performing turbo decoding operates on a hybrid serial/parallel concatenated code. 19. The iterative decoder of claim 15, wherein the means for performing turbo decoding operates on a turbo product code. 20. An iterative decoder, comprising: an internal code decoder operable to perform iterative decoding of a data block; and an external code decoder capable of supplying a feedback signal to the internal decoder; wherein the feedback signal is used to influence selective decisions during subsequent decoding iterations of the data block; and the internal code decoder comprises a turbo decoder that operates on at least one of a serial concatenated code, a parallel concatenated code, a hybrid serial/parallel concatenated code, and a turbo product code.