First and second complementary voltage signals are operatively coupled across a series circuit comprising first and second sense resistors and a circuit element therebetween. A DC bias current in the series circuit is substantially nulled, and an output signal responsive to the self-impedance of the
First and second complementary voltage signals are operatively coupled across a series circuit comprising first and second sense resistors and a circuit element therebetween. A DC bias current in the series circuit is substantially nulled, and an output signal responsive to the self-impedance of the circuit element is generated responsive at least one of a voltage across the first sense resistor and a voltage across the second sense resistor.
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What is claimed is: 1. A method of processing a signal responsive to a self-impedance of a circuit element, comprising: a. generating first and second complementary voltage signals, wherein said first and second complementary voltage signals comprise respective first and second oscillatory voltage
What is claimed is: 1. A method of processing a signal responsive to a self-impedance of a circuit element, comprising: a. generating first and second complementary voltage signals, wherein said first and second complementary voltage signals comprise respective first and second oscillatory voltage signals having a nominal peak amplitude, and said second oscillatory voltage signal comprises a waveform of said first oscillatory voltage signal shifted in phase by substantially 180 degrees; b. operatively coupling said first complementary voltage signal to a first node of a series circuit; c. operatively coupling said second complementary voltage signal to a fourth node of said series circuit, wherein said series circuit comprises: i) a first sense resistor between said first node and a second node; and ii) a second sense resistor between a third node and said fourth node, wherein said series circuit is completed by connecting said second and third nodes to the circuit element; d. detecting a signal responsive to a DC bias current in said series circuit; e. controlling at least one of said first and second complementary voltage signals so as to substantially null said signal responsive to said DC bias current in said series circuit; and f. generating an output signal responsive to at least one of a voltage across said first sense resistor and a voltage across said second sense resistor, wherein said output signal is responsive to the self-impedance of said circuit element when said circuit element is connected to said second and third nodes of said series circuit. 2. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising regulating a voltage across said second and third nodes in reference to a predetermined level, wherein the operations of regulating said voltage across said second and third nodes, and operatively coupling said first and second complementary voltage signals to said first and fourth nodes of said series circuit comprise: a. applying said first complementary voltage signal to an input of a first amplifier; b. operatively coupling said second node of said series circuit to said input of said first amplifier; c. applying said second complementary voltage signal to an input of a second amplifier; d. operatively coupling said third node of said series circuit to said input of said second amplifier; and e. operatively coupling an output of said second amplifier to said fourth node of said series circuit. 3. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 2, wherein said first amplifier comprises a first operational amplifier and said second amplifier comprises a second operational amplifier, further comprising: a. operatively coupling said first complementary voltage signal through a first input resistor to an inverting input of said first operational amplifier; b. operatively coupling said second node of said series circuit through a first feedback resistor to said inverting input of said first operational amplifier; c. operatively coupling said second complementary voltage signal through a second input resistor to an inverting input of said second operational amplifier; and d. operatively coupling said third node of said series circuit through a second feedback resistor to said inverting input of said second operational amplifier. 4. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 3, wherein said first complementary voltage signal comprises a first bias voltage signal, said second complementary voltage signal comprises a second bias voltage signal, said first and second bias voltage signals are substantially equal in value, and said first and second bias voltage signals are at least as great in value as said nominal peak amplitude of said first and second oscillatory voltage signals, further comprising: operatively coupling said first bias voltage signal to a non-inverting input of said first operational amplifier, and operatively coupling said second bias voltage signal to a non-inverting input of said second operational amplifier, wherein at least one of said first and second bias voltage signals is responsive to feedback from at least one of said second and third nodes, or at least one of said first and fourth nodes, of said series circuit. 5. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 4, wherein said second node of said series circuit is operatively coupled through a third feedback resistor to a non-inverting input of a fifth operational amplifier, said first bias voltage signal is operatively coupled through a third input resistor to said non-inverting input of said fifth operational amplifier, said third node of said series circuit is operatively coupled through a fourth feedback resistor to an inverting input of said fifth operational amplifier, an output of said fifth operational amplifier is operatively coupled through a fifth feedback resistor to said inverting input of said fifth operational amplifier, and said second bias voltage signal is generated by said output of said fifth operational amplifier. 6. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 4, wherein said second node of said series circuit is operatively coupled through a third feedback resistor to a non-inverting input of a fifth operational amplifier, said first bias voltage signal is operatively coupled through a third input resistor to said non-inverting input of said fifth operational amplifier, said third node of said series circuit is operatively coupled through a fourth feedback resistor to an inverting input of said fifth operational amplifier, an output of said fifth operational amplifier is operatively coupled through a fifth feedback resistor to said inverting input of said fifth operational amplifier, said output of said fifth operational amplifier is operatively coupled through a first capacitor to said inverting input of said fifth operational amplifier, and said second bias voltage signal is generated by said output of said fifth operational amplifier. 7. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 6, wherein said second bias voltage signal is generated by said output of said fifth operational amplifier through a first output resistor, wherein a first terminal of said first output resistor is operatively coupled to said output of said fifth operational amplifier, a second terminal of said first output resistor is operatively coupled to a ground through a second capacitor, and said second bias voltage signal is generated at said second terminal of said first output resistor. 8. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 6, wherein said non-inverting input of said fifth operational amplifier is operatively coupled to a ground through a third capacitor, and said inverting input of said fifth operational amplifier is operatively coupled to said ground through a fourth capacitor. 9. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 4, wherein said first node of said series circuit is operatively coupled through a third feedback resistor to a non-inverting input of a fifth operational amplifier, said first bias voltage signal is operatively coupled through a third input resistor to said non-inverting input of said fifth operational amplifier, said fourth node of said series circuit is operatively coupled through a fourth feedback resistor to an inverting input of said fifth operational amplifier, an output of said fifth operational amplifier is operatively coupled through a fifth feedback resistor to said inverting input of said fifth operational amplifier, and said second bias voltage signal is generated by said output of said fifth operational amplifier. 10. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 4, wherein said first node of said series circuit is operatively coupled through a third feedback resistor to a non-inverting input of a fifth operational amplifier, said first bias voltage signal is operatively coupled through a third input resistor to said non-inverting input of said fifth operational amplifier, said fourth node of said series circuit is operatively coupled through a fourth feedback resistor to an inverting input of said fifth operational amplifier, an output of said fifth operational amplifier is operatively coupled through a fifth feedback resistor to said inverting input of said fifth operational amplifier, said output of said fifth operational amplifier is operatively coupled through a first capacitor to said inverting input of said fifth operational amplifier, and said second bias voltage signal is generated by said output of said fifth operational amplifier. 11. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 10, wherein said second bias voltage signal is generated by said output of said fifth operational amplifier through a first output resistor, wherein a first terminal of said first output resistor is operatively coupled to said output of said fifth operational amplifier, a second terminal of said first output resistor is operatively coupled to ground through a second capacitor, and said second bias voltage signal is generated at said second terminal of said first output resistor. 12. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 10 wherein said non-inverting input of said fifth operational amplifier is operatively coupled to a ground through a third capacitor, and said inverting input of said fifth operational amplifier is operatively coupled to said ground through a fourth capacitor. 13. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 4, wherein said second node of said series circuit is operatively coupled through a third feedback resistor to a non-inverting input of a fifth operational amplifier, said third node of said series circuit is operatively coupled through a fourth feedback resistor to an inverting input of said fifth operational amplifier, an output of said fifth operational amplifier is operatively coupled through a feedback capacitor to said inverting input of said fifth operational amplifier, said non-inverting input of said fifth operational amplifier is operatively coupled to a ground through a third capacitor; and said inverting input of said fifth operational amplifier is operatively coupled to said ground through a fourth capacitor, and said second bias voltage signal is generated by said output of said fifth operational amplifier through a second output resistor. 14. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 13, wherein the operation of operatively coupling said first bias voltage signal to said non-inverting input of said first operational amplifier comprises operatively coupling said first bias voltage signal to said non-inverting input of said first operational amplifier through a voltage divider; and the operation of operatively coupling said second bias voltage signal to said non-inverting input of said second operational amplifier comprises operatively coupling said second bias voltage signal to said non-inverting input of said second operational amplifier through a fourth input resistor. 15. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 3, further comprising buffering a second node signal at said second node so as to form a buffered second node signal, wherein the operation of operatively coupling said second node through said first feedback resistor to said inverting input of said first operational amplifier comprises operatively coupling said buffered second node signal to a first terminal of said first feedback resistor, and operatively coupling a second terminal of said first feedback resistor to said inverting input of said first operational amplifier; and buffering a third node signal at said third node so as to form a buffered third node signal, wherein the operation of operatively coupling said third node through said second feedback resistor to said inverting input of said second operational amplifier comprises operatively coupling said buffered third node signal to a first terminal of said second feedback resistor, and operatively coupling a second terminal of said second feedback resistor to said inverting input of said second operational amplifier. 16. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 15, wherein the operation of buffering said second node signal at said second node comprises operatively coupling said second node of said series circuit to a non-inverting input of a third operational amplifier; and operatively coupling an inverting input of said third operational amplifier to an output of said third operational amplifier, wherein said buffered second node signal is generated at said output of said third operational amplifier; and the operation of buffering said third node signal at said third node comprises operatively coupling said third node of said series circuit to a non-inverting input of a fourth operational amplifier; and operatively coupling an inverting input of said fourth operational amplifier to an output of said fourth operational amplifier, wherein said buffered third node signal is generated at said output of said fourth operational amplifier. 17. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 4, wherein said first complementary voltage signal comprises a first bias voltage signal, said second complementary voltage signal comprises a second bias voltage signal, said first and second bias voltage signals are substantially equal in value, and said first and second bias voltage signals are at least as great in value as said nominal peak amplitude of said first and second oscillatory voltage signals, further comprising: operatively coupling said first bias voltage signal to a non-inverting input of said first operational amplifier, and operatively coupling said second bias voltage signal to a non-inverting input of said second operational amplifier, wherein at least one of said first and second bias voltage signals is responsive to feedback from at least one of said first and fourth nodes of said series circuit. 18. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 3, wherein a gain of said first amplifier is substantially unity, and a gain of said second amplifier is substantially unity. 19. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein the operation of generating said output signal further comprises generating said output signal responsive to at least one test signal, and said test signal provides for simulating a condition of the circuit element. 20. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 19, wherein said at least one test signal comprises first and second test signals, and said first and second test signals are associated with different terminals of a common signal generator. 21. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising band-pass filtering said output signal from said operational amplifier, wherein a frequency range of a pass-band of an associated band-pass filter is adjusted responsive to an operating frequency of said first and second oscillatory voltage signals. 22. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising demodulating said output signal, or a signal responsive thereto, so as to generate at least one of a first in-phase signal and a first quadrature-phase signal, wherein said first in-phase signal is in-phase with said first or second oscillatory voltage signal and is responsive to an in-phase component thereof, and said first quadrature-phase signal component is substantially 90 degrees out-of-phase with respect to said first or second oscillatory voltage signal and is responsive to a quadrature-phase component thereof. 23. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 22, further comprising at least one of filtering said first in-phase signal with a first band-pass filter so as to generate a second in-phase signal, and filtering said first quadrature-phase signal with a second band-pass filter so as to generate a second quadrature-phase signal. 24. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, further comprising detecting if a magnitude of said output signal, or a signal responsive thereto, is greater than unity, and indicating an error condition if said magnitude of said output signal, or said signal responsive thereto, is greater than unity. 25. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein said circuit element comprises at least one inductance coil. 26. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 25, further comprising operatively coupling said at least one inductance coil to a magnetic circuit of a vehicle; and detecting a perturbation of said magnetic circuit responsive to said output signal. 27. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 26, wherein the operation of detecting said perturbation of said magnetic circuit comprises detecting a crash of said vehicle, wherein said perturbation of said magnetic circuit is responsive to said crash. 28. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 27, further comprising controlling a safety restraint system responsive to said output signal. 29. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 28, further comprising: a. demodulating said output signal, or a signal responsive thereto, so as to generate at least one of a first in-phase signal and a first quadrature-phase signal, wherein said first in-phase signal is in-phase with said first or second oscillatory voltage signal and is responsive to an in-phase component thereof, and said first quadrature-phase signal is substantially 90 degrees out-of-phase with respect to said first or second oscillatory voltage signal and is responsive to a quadrature-phase component thereof; and b. controlling a safety restraint actuator of said safety restraint system responsive to at least one of said first in-phase signal, said first quadrature-phase signal. 30. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 1, wherein the operation of generating an output signal comprises: a. operatively coupling said first node through a first resistor to a first input of an operational amplifier; b. operatively coupling said second node through a second resistor to a second input of said operational amplifier; c. operatively coupling said third node through a third resistor to said first input of said operational amplifier; d. operatively coupling said fourth node through a fourth resistor to said second input of said operational amplifier; e. operatively coupling a non-inverting input of said operational amplifier through a fifth resistor to an AC ground; and f. operatively coupling an inverting input of said operational amplifier through a sixth resistor to an output of said operational amplifier, wherein said first input of said operational amplifier comprises one of said non-inverting input and said inverting input, said second input of said operational amplifier comprises the other of said inverting input and said non-inverting input, and said output signal is generated by said output of said operational amplifier. 31. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 30, further comprising at least one of detecting if a magnitude of a signal across said first sense resistor is less than a threshold, and detecting if a magnitude of a signal across said second sense resistor is less than said threshold; and indicating an error condition if either said signal across said first sense resistor is less than said threshold, or if said signal across said second sense resistor is less than said threshold. 32. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 22, further comprising representing at least one of said first in-phase signal and said first quadrature-phase signal in digital form. 33. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 32, wherein the operations of demodulating said output signal, or a signal responsive thereto, and representing at least one of said first in-phase signal and said first quadrature-phase signal in digital form comprise: a. transforming said output signal, or said signal responsive thereto, with a sigma-delta converter, so as to generate a first intermediate signal; b. at least one of mixing a sinusoidal signal with said first intermediate signal so as to generate a first in-phase intermediate signal, and mixing a cosinusoidal signal with said first intermediate signal so as to generate a first quadrature-phase intermediate signal, wherein said sinusoidal signal is in-phase with said first oscillatory voltage signal, and said cosinusoidal signal is substantially 90 degrees out-of-phase with respect to said first oscillatory voltage signal; and c. at least one of filtering said first in-phase intermediate signal with a first decimation filter and a first low-pass filter so as to generate said first in-phase signal; and filtering said first quadrature-phase intermediate signal with a second decimation filter and a second low-pass filter so as to generate said first quadrature-phase signal. 34. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 33, wherein said output signal, or said signal responsive thereto, is adapted so that a magnitude thereof when input to said sigma-delta converter is less than unity under normal operating conditions. 35. A method of processing a signal responsive to a self-impedance of a circuit element as recited in claim 29, further comprising representing at least one of said first in-phase signal and said first quadrature-phase signal in digital form, wherein the operations of demodulating said output signal, or a signal responsive thereto, and representing at least one of said first in-phase signal and said first quadrature-phase signal in digital form comprise: a. transforming said output signal, or said signal responsive thereto, with a sigma-delta converter, so as to generate a first intermediate signal; b. at least one of mixing a sinusoidal signal with said first intermediate signal so as to generate a first in-phase intermediate signal, and mixing a cosinusoidal signal with said first intermediate signal so as to generate a first quadrature-phase intermediate signal, wherein said sinusoidal signal is in-phase with said first oscillatory voltage signal, and said cosinusoidal signal is substantially 90 degrees out-of-phase with respect to said first oscillatory voltage signal; and c. at least one of filtering said first in-phase intermediate signal with a first decimation filter and a first low-pass filter so as to generate said first in-phase signal; and filtering said first quadrature-phase intermediate signal with a second decimation filter and a second low-pass filter so as to generate said first quadrature-phase signal, further comprising controlling said safety restraint actuator responsive to at least said first in-phase signal.
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