IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
UP-0699081
(2007-01-29)
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등록번호 |
US-7578282
(2009-09-08)
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우선권정보 |
JP-2006-019270(2006-01-27) |
발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
4 인용 특허 :
8 |
초록
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In a knock sensor signal processing apparatus, a first apparatus which receives an engine knock sensor signal performs A/D conversions of the signal with a predetermined period and transmits successive pluralities of A/D values in parallel, by serial data communication, to a second apparatus in resp
In a knock sensor signal processing apparatus, a first apparatus which receives an engine knock sensor signal performs A/D conversions of the signal with a predetermined period and transmits successive pluralities of A/D values in parallel, by serial data communication, to a second apparatus in response to respective commands received from the second apparatus. The number of communication lines provided for transmitting the A/D values is made greater than those for transmitting commands from the second apparatus to the first apparatus, so that a high A/D conversion frequency together with low data rate of transmitting the A/D values can be achieved, thereby reducing communication-generated noise.
대표청구항
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What is claimed is: 1. A knock sensor signal processing apparatus comprising: a first apparatus coupled to receive a knock sensor signal that is an analog signal produced from a knock sensor of a vehicle engine and to produce a corresponding digital signal produced from an A/D (analog-to-digital) c
What is claimed is: 1. A knock sensor signal processing apparatus comprising: a first apparatus coupled to receive a knock sensor signal that is an analog signal produced from a knock sensor of a vehicle engine and to produce a corresponding digital signal produced from an A/D (analog-to-digital) converter; and a second apparatus coupled for bit-serial communication of said digital signals from said first apparatus via bit-serial communication lines; wherein said A/D converter of said first apparatus performs repetitive A/D conversions of said knock sensor signal with a predetermined conversion period, and successive A/D values resulting from said A/D conversions being transmitted bit-serially from said first apparatus to said second apparatus via said bit-serial communication lines; wherein said second apparatus comprises digital filter processing circuitry for performing consecutive digital filter processing of successive ones of said A/D values; wherein said bit-serial communication lines comprise a first set of bit-serial communication lines for transmitting at least said A/D values from said first apparatus to said second apparatus and a second set of communication lines for transmitting at least operating commands from said second apparatus to said first apparatus; and wherein said first set of bit-serial communication lines is greater in number than said second set of communication lines whereby the frequency of signals used for data communication passing from said first apparatus to said second apparatus is reduced by the reciprocal of the number of bit serial communication lines in said first set. 2. A knock sensor signal processing apparatus according to claim 1, wherein: designating a number of bit-serial communication lines constituting said first set of bit-serial communication lines as n, where n is an integer of value 2 or higher, said first apparatus assigns respective ones of a set of n successively derived A/D values of said knock sensor signal to be transmitted via predetermined respective ones of said first set of bit-serial communication lines, and said set of n A/D values are simultaneously transmitted to said second apparatus, by bit-serial communication via respective ones of said bit-serial communication lines, within a single communication interval. 3. A knock sensor signal processing apparatus according to claim 2, wherein: designating said predetermined conversion period as T time units, said first apparatus transmits a set of said n A/D values once in every (n×T) time units. 4. A knock sensor signal processing apparatus according to claim 2, wherein: said second apparatus comprises circuitry adapted to detect failure of one of said first set of bit-serial communication lines and to respond to said failure by initiating a change from a normal mode of operation to a fail-safe mode of operation in which said digital filter processing is executed without utilizing A/D values that are transmitted via said communication line for which failure has occurred. 5. A knock sensor signal processing apparatus according to claim 4, wherein: said digital filter processing is executed by calculations utilizing a set of filter coefficients, and said second apparatus comprises circuitry adapted to respond to initiation of said fail-safe mode by changing said filter coefficients from a first set thereof which are predetermined for use during said normal mode to a second set thereof which are predetermined for use during said fail-safe mode. 6. A knock sensor signal processing apparatus according to claim 2, wherein: said second apparatus is selectively operable in a first operating mode and a second operating mode in accordance with an operating condition of said engine, in said first operating mode, said digital filter processing is applied to each of said successive sets of A/D values that are respectively received via said n bit-serial communication lines, and in said second operating mode, said digital filter processing is omitted from being applied to A/D values that are received via at least a predetermined one of said n bit-serial communication lines, and said second apparatus comprises circuitry adapted to respond to operation in said first mode by selecting a first set of filter coefficients that are predetermined for use in digital filter processing in said first mode, and to respond to operation in said second mode by selecting a second set of filter coefficients, that are predetermined for use in digital filter processing in said second mode. 7. A knock sensor signal processing apparatus according to claim 1, wherein: said first set of bit-serial communication lines comprise at least one pair of bit-serial communication lines that are disposed adjacent to one another, and for each of respective pairs of data sets that are to be transmitted from said first apparatus to said second apparatus, said first apparatus transmits a first data set of a pair thereof via a first one of said pair of bit-serial communication lines in a bit sequence which begins from a most significant bit position of said first data set, and transmits the second data set of said pair thereof via a second one of said pair of bit-serial communication lines, in a bit sequence which begins from a least significant bit position of said second data set. 8. A knock sensor signal processing apparatus according to claim 1, wherein: said first set of bit-serial communication lines comprise at least one pair of bit-serial communication lines that are disposed adjacent to one another, a plurality of respectively different types of data sets are transmitted from said first apparatus to said second apparatus via said first set of bit-serial communication lines, with a predetermined plurality of bits within each of said data sets constitute a discrimination code for indicating said type, and when said first apparatus simultaneously transmits a pair of data sets via respective ones of said pair of bit-serial communication lines, respective arrangements of bits constituting said discrimination codes of said pair of data sets are made different from one another. 9. A knock sensor signal processing apparatus according to claim 1, wherein: each time said second apparatus has received m A/D values from said first apparatus, where m is an integer of 2 or greater, said second apparatus performs consecutive digital filter processing operations on said m A/D values. 10. A knock sensor signal processing apparatus according to claim 9, wherein: said second apparatus comprises a memory having stored therein a set of M filter coefficients for use in executing said digital filter processing operations, where M is an integer of 2 or greater, and when said second apparatus performs said successive digital filter processing operations on a received set of m A/D values, a total number of times that said set of filter coefficients are read out from said memory for use in executing said filter processing operations is less than (m×M). 11. A knock sensor signal processing apparatus according to claim 1, wherein: said first apparatus and said second apparatus respectively comprise a first integrated circuit and a second integrated circuit. 12. A knock sensor signal processing apparatus according to claim 11, wherein: said first integrated circuit comprises a digital processor configured to have at least functions for controlling said A/D converter and for controlling communication with said second integrated circuit, and said second integrated circuit comprises a digital processor configured to have at least functions for controlling said digital filter processing circuitry and for controlling communication with said first integrated circuit. 13. A method for transmitting and processing knock sensor signal data, said method comprising: receiving at a first apparatus a knock sensor signal that is an analog signal produced from a knock sensor of a vehicle engine and producing a corresponding digital signal produced from an A/D (analog-to-digital) converter; bit-serial communicating said digital signals from said first apparatus to a second apparatus via bit-serial communication lines; wherein said A/D converter of said first apparatus performs repetitive A/D conversions of said knock sensor signal with a predetermined conversion period, and successive A/D values resulting from said A/D conversions being transmitted bit-serially from said first apparatus to said second apparatus via said bit-serial communication lines; wherein said second apparatus comprises digital filter processing circuitry for performing consecutive digital filter processing of successive ones of said A/D values; wherein said bit-serial communication lines comprise a first set of bit-serial communication lines for transmitting at least said A/D values from said first apparatus to said second apparatus and a second set of communication lines for transmitting at least operating commands from said second apparatus to said first apparatus; and wherein said first set of bit-serial communication lines is greater in number than said second set of communication lines whereby the frequency of signals used for data communication passing from said first apparatus to said second apparatus is reduced by the reciprocal of the number of bit serial communication lines in said first set. 14. The method of claim 13, wherein: designating a number of bit-serial communication lines constituting said first set of bit-serial communication lines as n, where n is an integer of value 2 or higher, said first apparatus assigns respective ones of a set of n successively derived A/D values of said knock sensor signal to be transmitted via predetermined respective ones of said first set of bit-serial communication via respective ones of said bit-serial communication lines, within a single communication interval. 15. The method of claim 14, wherein: designating said predetermined conversion period as T time units, said first apparatus transmits a set of said n A/D values once in every (n×T) time units. 16. The method of claim 14, wherein: said second apparatus comprises circuitry adapted to detect failure of one of said first set of bit-serial communication lines and to respond to said failure by initiating a change from a normal mode of operation to a fail-safe mode of operation in which said digital filter processing is executed without utilizing A/D values that are transmitted via said communication line for which failure has occurred. 17. The method of claim 16, wherein: said digital filter processing is executed by calculations utilizing a set of filter coefficients, and said second apparatus comprises circuitry adapted to respond to initiation of said fail-safe mode by changing said filter coefficients from a first set thereof which are predetermined for use during said normal mode to a second set thereof which are predetermined for use during said fail-safe mode. 18. The method of claim 14, wherein: said second apparatus is selectively operable in a first operating mode and a second operating mode in accordance with an operating condition of said engine, in said first operating mode, said digital filter processing is applied to each of said successive sets of A/D values that are respectively received via said n bit-serial communication lines, and in said second operating mode, said digital filter processing is omitted from being applied to A/D values that are received via at least a predetermined one of said n bit-serial communication lines, and said second apparatus comprises circuitry adapted to respond to operation in said first mode by selecting a first set of filter coefficients that are predetermined for use in digital filter processing in said first mode, and to respond to operation in said second mode by selecting a second set of filter coefficients, that are predetermined for use in digital filter processing in said second mode. 19. The method of claim 13, wherein: said first set of bit-serial communication lines comprise at least one pair of bit-serial communication lines that are disposed adjacent to one another, and for each of respective pairs of data sets that are to be transmitted from said first apparatus to said second apparatus, said first apparatus transmits a first data set of a pair thereof via a first one of said pair of bit-serial communication lines in a bit sequence which begins from a most significant bit position of said first data set, and transmits the second data set of said pair thereof via a second one of said pair of bit-serial communication lines, in a bit sequence which begins from a least significant bit position of said second data set. 20. The method of claim 13, wherein: said first set of bit-serial communication lines comprise at least one pair of bit-serial communication lines that are disposed adjacent to one another, a plurality of respectively different types of data sets are transmitted from said first apparatus to said second apparatus via said first set of bit-serial communication lines, with a predetermined plurality of bits within each of said data sets constitute a discrimination code for indicating said type, and when said first apparatus simultaneously transmits a pair of data sets via respective ones of said pair of bit-serial communication lines, respective arrangements of bits constituting said discrimination codes of said pair of data sets are made different from one another. 21. The method of claim 13, wherein: each time said second apparatus has received m A/D values from said first apparatus, where m is an integer of 2 or greater, said second apparatus performs consecutive digital filter processing operations on said m A/D values. 22. The method of claim 21, wherein: said second apparatus comprises a memory having stored therein a set of M filter coefficients for use in executing said digital filter processing operations, where M is an integer of 2 or greater, and when said second apparatus performs said successive digital filter processing operations on a received set of m A/D values, a total number of times that said set of filter coefficients are read out from said memory for use in executing said filter processing operations is less than (m×M). 23. The method of claim 13, wherein: said first apparatus and said second apparatus respectively comprise a first integrated circuit and a second integrated circuit. 24. The method of claim 23, wherein: said first integrated circuit comprises a digital processor configured to have at least functions for controlling said A/D converter and for controlling communication with said second integrated circuit, and said second integrated circuit comprises a digital processor configured to have at least functions for controlling said digital filter processing circuitry and for controlling communication with said first integrated circuit.
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