IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0721902
(2005-12-08)
|
등록번호 |
US-7579884
(2009-09-08)
|
우선권정보 |
FR-04 13352(2004-12-15) |
국제출원번호 |
PCT/FR05/003081
(2005-12-08)
|
§371/§102 date |
20070924
(20070924)
|
국제공개번호 |
WO06/064110
(2006-06-22)
|
발명자
/ 주소 |
|
출원인 / 주소 |
- Commissariat a l'Energie Atomique
|
대리인 / 주소 |
Brinks Hofer Gilson & Lione
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
7 |
초록
▼
A frequency doubler circuit includes first and second arrangements of switches connected to the positive and negative inputs of a comparator, respectively, and arranged in such a way that first and third voltages during the first phase of a reference clock signal and second and fourth voltages durin
A frequency doubler circuit includes first and second arrangements of switches connected to the positive and negative inputs of a comparator, respectively, and arranged in such a way that first and third voltages during the first phase of a reference clock signal and second and fourth voltages during a second phase opposite to the first phase are applied to the positive and negative inputs, where the first and second voltages and the third and fourth voltages are shifted with respect to each other at a half-period of the reference clock signal and the ratio between slopes of the voltages is fixed with respect to a selected current.
대표청구항
▼
The invention claimed is: 1. A frequency doubler device configured to receive an input signal at a reference frequency and to deliver an output clock signal having a frequency twice that of the reference frequency and having a chosen duty cycle, the frequency doubler device comprising an exclusive
The invention claimed is: 1. A frequency doubler device configured to receive an input signal at a reference frequency and to deliver an output clock signal having a frequency twice that of the reference frequency and having a chosen duty cycle, the frequency doubler device comprising an exclusive OR gate having a first input receiving a first clock signal at the reference frequency, a second input receiving a second clock signal at the same frequency as the first clock signal and offset relative to said first clock signal by a chosen offset determining the duty cycle, and an output delivering the output clock signal with a frequency twice the reference frequency; wherein the device further comprises a first block comprising: a D flip-flop having a D input, an output linked to the second input of the exclusive OR gate to apply the second clock signal to the input, and an inverse output linked to the D input, a comparator having a positive input, a negative input and an output controlling the D flip-flop, first and second arrangements of switches respectively linked to the positive and negative inputs of the comparator, and controlled by a first control signal substantially in phase with the input signal and a second control signal at least partially the reverse of the first control signal to apply respectively, to said positive and negative inputs, either first and third voltages, or second and fourth voltages, wherein the first, second, third and fourth voltages are voltage ramps, four voltage ramp generation devices for the first, second, third and fourth voltages, each voltage ramp generation device comprising a current source in series with a capacitor between a power supply voltage and a reference voltage and a reset switch in parallel with the capacitor, the current sources of the third and fourth voltage ramp generation devices presenting a current ratio k relative to the current sources of the first and second voltage ramp generation devices, wherein the opening of the reset switches of the first and fourth voltage ramp generation devices and the opening of the reset switches of the second and third voltage ramp generation devices being controlled by third and fourth control signals substantially the reverse of each other and in phase or in phase opposition with the first and second control signals, wherein the first and second voltages relative to the third and fourth voltages are offset by a half-period of the input signal, and wherein the ratio of the slopes of the first and second voltage ramps relative to the slopes of the third and fourth voltage ramps are determined by the chosen current ratio (k), where the current ratio is chosen according to the chosen duty cycle. 2. The device according to claim 1, wherein the first clock signal applied to the exclusive OR gate and the fourth control signal comprise the same signal. 3. The device according to claim 1, further comprising a second block, wherein the first clock signal applied to the exclusive OR gate is generated by the second block, and wherein the second block comprises a comparator, a flip-flop, arrangements of switches and voltage ramp generation devices, wherein the first and second blocks are connected to a control signal generation block receiving the input signal and delivering the first, second, third, and fourth control signals from the input signal. 4. The device according to claim 1, wherein the first and second control signals are non-overlapping clock signals. 5. The device according to claim 1 further comprising first and second chains of NOT gates preceded by a NOR gate and a NAND gate, respectively, wherein the input signal is applied to a first input of the NOR and NAND gates, respectively, wherein the output of the first chain is applied to a second input of the NAND gate and the output of the second chain is applied to a second input of the NOR gate. 6. The device according to claim 5, wherein the fourth control signal is delivered by a delay cell receiving the second control signal. 7. The device according to claim 6, wherein the third control signal is delivered by a NOT gate receiving the fourth control signal. 8. The device according to claim 1, wherein the first arrangement of switches comprises first and second switches respectively receiving the first and second voltages, and the outputs of which are connected to the positive input of the comparator, wherein the second arrangement of switches comprises third and fourth switches respectively receiving the third and fourth voltages, and the outputs of which are connected to the negative input of the comparator, and wherein the first and third switches are controlled by the first control signal and the third and fourth switches are controlled by the second control signal. 9. The device according to claim 1, wherein the reset switch of the first voltage ramp generation device is controlled by the third control signal and the reset switch of the second ramp voltage generation device is controlled by the fourth control signal. 10. The device according to claim 1, wherein the reset switches of the third and fourth voltage generation devices are controlled by signals delivered by AND gates to which are applied the output signal from the comparator and, respectively, the third and fourth control signals. 11. A magnetic field measuring circuit comprising a flux-gate magnetic sensor produced in microelectronic technology, an electronic excitation circuit of the sensor receiving an input signal, and a synchronous detection system comprising a frequency doubler device according to any one of claims 1 to 10, to which the input signal is applied.
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