초록 ▼

A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids.

A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

대표청구항 ▼

What is claimed is: 1. A method of filling an opening comprising: providing a substrate prepared with a dielectric layer with an opening with upper and lower portions, the opening having an aspect ratio; forming a metal barrier layer, the metal barrier layer lining the sides and bottom of the openi

What is claimed is: 1. A method of filling an opening comprising: providing a substrate prepared with a dielectric layer with an opening with upper and lower portions, the opening having an aspect ratio; forming a metal barrier layer, the metal barrier layer lining the sides and bottom of the opening in the dielectric layer; forming a copper seed layer on the metal barrier layer; forming a non-conformal first copper layer in only the lower portion of the opening to partially fill the opening, wherein the first copper layer forms on the seed layer and includes a planar top surface, wherein the first copper layer reduces the aspect ratio of the opening; using ECP to form a second copper layer to fill the reduced aspect ratio opening, wherein the first and second fill processes are different types of fill processes, the second copper layer contacts the top surface of the first copper layer; annealing the substrate; and polishing the substrate to form a planar surface with the top of the opening. 2. A method of forming integrated circuits comprising: providing a substrate prepared with a dielectric layer having an opening with an aspect ratio, the opening includes upper and lower portions; forming a conductive seed layer to line sides of the upper and lower portions and bottom of the opening; forming a first conductive layer in a first fill process, wherein the first conductive layer forms only in the lower portion of the opening to partially fill the opening to reduce the aspect ratio of the opening, wherein the first conductive layer forms on sides and bottom of the seed layer in the lower portion of the opening and includes a planar top surface; and forming a second conductive layer in a second fill process to fill the reduced aspect ratio opening, wherein the second conductive layer contacts the first conductive layer. 3. The method of claim 2 wherein forming the first conductive layer in the first fill process comprises electroless plating with a solution which includes using water jet or spin on technology, wherein parameters of the electroless plating are tuned to form the first conductive layer in the lower portion of the opening. 4. The method of claim 2 wherein: the opening comprises a dual damascene opening which includes a via below a trench, the trench being wider than the via; and forming the first conductive layer in the first fill process comprises electroless plating with a solution which includes using water jet or spin on technology, wherein parameters of the electroless plating are tuned to form the first conductive layer in the lower portion of the opening to at least partially fill the via. 5. The method of claim 4 wherein the first conductive layer fills the lower portion of the opening to fill the via. 6. The method of claim 2 wherein the first and second conductive layers comprise copper. 7. The method of claim 6 wherein forming the second conductive layer comprises electroplating and forms the second conductive layer over the first conductive layer and filling the opening. 8. The method of claim 7 further comprises polishing to remove excess second conductive layer to provide a planar surface with the top of the opening. 9. The method of claim 2 wherein forming the second conductive layer comprises electroplating and forms the second conductive layer over the first conductive layer and filling the opening. 10. The method of claim 9 further comprises polishing to remove excess second conductive layer to provide a planar surface with the top of the opening. 11. A method of forming interconnects in an integrated circuit comprising: providing a substrate prepared with an intermetal dielectric layer having an opening with upper and lower portions, the lower portion includes a via and the upper portion includes a trench, the opening having an aspect ratio; forming a seed layer to line sides and bottom of the opening; forming a first conductive layer in a first fill process by electroless plating, the first fill process forms the conductive layer only in the lower portion of the opening to partially fill the opening, wherein the first conductive layer forms on sides and bottom of the seed layer in the lower portion and includes a planar top surface, the partial fill reduces the aspect ratio of the opening; and forming a second conductive layer in a second fill process to fill the reduced aspect ratio opening. 12. A method of forming interconnects in an integrated circuit comprising: providing a substrate prepared with a dielectric layer having a dual damascene opening with upper and lower portions, the dual damascene opening includes a via below a trench, wherein the trench is wider than the via, the dual damascene opening having an aspect ratio; forming a seed layer to line sidewalls in the upper and lower portions and bottom of the dual damascene opening; forming a first conductive layer in a first fill process, the first fill process forms the first conductive layer in only the lower portion of the dual damascene opening to partially fill the dual damascene opening, wherein the first conductive layer forms on sides and on bottom of the seed layer in the lower portion of the dual damascene opening and includes a planar top surface, the first fill process reduces the aspect ratio of the dual damascene opening; and forming a second conductive layer in a second fill process to fill the reduced aspect ratio dual damascene opening with conductive material, the second conductive layer contacts the planar top surface of the first conductive layer.