초록 ▼

An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from th

An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of common DSP functional blocks such as multiplier-accumulator (MAC) blocks may be improved. Delays may be further reduced by combining analysis operations with write or move operations.

대표청구항 ▼

What is claimed is: 1. A method for processing signals on an integrated circuit device that includes a plurality of logic regions, the method comprising: configuring at least one of the logic regions as word conditioning logic; configuring at least another one of the logic regions as a computation

What is claimed is: 1. A method for processing signals on an integrated circuit device that includes a plurality of logic regions, the method comprising: configuring at least one of the logic regions as word conditioning logic; configuring at least another one of the logic regions as a computation unit having an input, an output, and a critical path, wherein the computation unit is configured to propagate signals from the input to the output via the critical path without propagating the signals through the word conditioning logic; and providing a datapath from the output of the computation unit to a storage destination, wherein signals on the datapath are propagated through the word conditioning logic. 2. The method defined in claim 1, further comprising: providing rounding logic in the word conditioning logic. 3. The method defined in claim 1, further comprising: providing saturation logic in the word conditioning logic. 4. The method defined in claim 1, further comprising: providing rounding logic and saturation logic in the word conditioning logic, wherein the rounding logic and the saturation logic are arranged in series. 5. The method defined in claim 4, further comprising: monitoring the signals in the computation unit using the saturation logic. 6. The method defined in claim 5, wherein the monitoring is performed by monitoring circuitry included in the saturation logic, wherein the monitoring circuitry is operated separately from and in parallel with the computation unit. 7. An integrated circuit device, comprising: logic configured as a computation unit having an input, an output, and a critical path, wherein the computation unit is configured to propagate signals received on the input to the output via the critical path without propagating the signals through word conditioning logic; and a datapath configured to convey output signals from the computation unit to a storage destination, wherein the output signals on the datapath are propagated through word conditioning logic. 8. The device defined in claim 7, wherein the computation unit includes an arithmetic logic unit in the critical path, wherein the arithmetic logic unit does not include word conditioning logic. 9. The device defined in claim 7, wherein the computation unit includes an accumulator in the critical path, wherein the accumulator does not include word conditioning logic. 10. The device defined in claim 7, further comprising: a first logic substructure containing word conditioning logic and having an associated input and an associated output, wherein the associated input of the first logic substructure is coupled to the output of the computation unit and the associated output of the first logic substructure is coupled to the datapath. 11. The device defined in claim 10, wherein the word conditioning logic contained in the first logic substructure is configured to perform rounding and saturation operations. 12. The device defined in claim 7, further comprising: a plurality of memory circuits, wherein the storage destination is at least one of the plurality of memory circuits. 13. The device defined in claim 7, further comprising: a plurality of registers, wherein the storage destination is at least one of the plurality of registers. 14. A digital processing system, comprising: processing circuitry; a system memory coupled to said processing circuitry; and the device defined in claim 7 coupled to the processing circuitry and the system memory. 15. A printed circuit board on which is mounted the device defined in claim 7. 16. The printed circuit board defined in claim 15, further comprising: a board memory mounted on the printed circuit board and coupled to the device. 17. The printed circuit board defined in claim 15, further comprising: processing circuitry mounted on the printed circuit board and coupled to the device. 18. An integrated circuit device including a plurality of logic regions, the device comprising: a storage circuit; at least one of the logic regions configured as a data conditioning and analysis circuit; at least another of the logic regions configured as a computation circuit having an input, an output, and a critical path, wherein the computation circuit is configured to propagate signals received on the input to the output via the critical path without propagating the signals through the data conditioning and analysis circuit, and wherein the computation circuit is programmably selectively configurable to perform at least one arithmetic operation on input data supplied from the storage circuit to produce output data; and a datapath configured to convey the output data from the computation circuit to the storage circuit, wherein the output data on the datapath are propagated through the data conditioning and analysis circuit. 19. The device defined in claim 18, wherein the data conditioning and analysis circuit comprises at least one word conditioning subcircuit and at least one analysis subcircuit. 20. A digital processing system, comprising: processing circuitry; a system memory coupled to said processing circuitry; and the device defined in claim 18 coupled to the processing circuitry and the system memory. 21. A printed circuit board on which is mounted the device defined in claim 18. 22. The printed circuit board defined in claim 21, further comprising: a board memory mounted on the printed circuit board and coupled to the device. 23. The printed circuit board defined in claim 21, further comprising: processing circuitry mounted on the printed circuit board and coupled to the device.