[특허]Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain

Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/46 H01L-021/02
출원번호	UP-0128628 (2005-05-13)
등록번호	US-7588994 (2009-09-24)
발명자 / 주소	Langdo, Thomas A. Currie, Matthew T. Hammond, Richard Lochtefeld, Anthony J. Fitzgerald, Eugene A.
출원인 / 주소	AmberWave Systems Corporation
대리인 / 주소	Goodwin Procter LLP
인용정보	피인용 횟수 : 11 인용 특허 : 258

초록

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

대표청구항 ▼

What is claimed is: 1. A method for forming a structure, the method comprising: forming an unstrained semiconductor layer over a first substrate; thereafter mechanically inducing strain in the unstrained semiconductor layer to define a first strained semiconductor layer; bonding the first strained semiconductor layer directly to an insulator layer disposed on a second substrate; and removing the first substrate from the first strained semiconductor layer, the strained semiconductor layer remaining bonded to the insulator layer. 2. The method of claim 1, wherein the first strained semiconductor layer is tensilely strained. 3. The method of claim 1, wherein the first strained semiconductor layer is compressively strained. 4. The method of claim 1, wherein the first strained semiconductor layer comprises at least one of silicon and germanium. 5. The method of claim 4, wherein the first strained semiconductor layer comprises approximately 100% silicon. 6. The method of claim 4, wherein the first strained semiconductor layer comprises approximately 100% germanium. 7. The method of claim 1, further comprising: defining a transistor over the second substrate, the transistor including a gate disposed above the first strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound. 8. The method of claim 7, wherein defining the transistor includes defining a gate dielectric layer over first strained semiconductor layer, such that the gate dielectric layer is disposed between the first strained semiconductor layer and the gate. 9. The method of claim 8, wherein defining the gate dielectric layer comprises atomic layer deposition. 10. The method of claim 1, wherein the first strained semiconductor layer has a misfit dislocation density of less than about 105 cm/cm2 after the first substrate is removed. 11. The method of claim 1, wherein the first strained semiconductor layer has a threading dislocation density selected from the range of about 10 dislocations/cm2 to about 107 dislocations/cm2 after the first substrate is removed. 12. The method of claim 1, wherein the first strained semiconductor layer has a surface roughness selected from the range of approximately 0.01 nm to approximately 1 nm after the first substrate is removed. 13. The method of claim 1, wherein the first strained semiconductor layer has a thickness uniformity across the substrate of better than approximately ±10% after the first substrate is removed. 14. The method of claim 1, wherein the first strained semiconductor layer has a thickness of less than approximately 200 Å after the first substrate is removed. 15. The method of claim 1, wherein the first strained semiconductor layer has a surface germanium concentration of less than approximately 1×1012 atoms/cm2 after the first substrate is removed. 16. The method of claim 1, wherein the first strained semiconductor layer has a density of bonding voids of less than 0.3 voids/cm2 after the first substrate is removed. 17. The method of claim 1, wherein the first strained semiconductor layer comprises at least one of a group II, a group III, a group V, and a group VI element. 18. The method of claim 1, further comprising: planarizing the first strained semiconductor layer after the first substrate is removed. 19. The method of claim 1, wherein bonding the first strained semiconductor layer to the insulator layer comprises plasma activating at least one of a top surface of the first strained semiconductor layer and a top surface of the insulator layer. 20. The method of claim 1, further comprising: forming a cleave plane between the first strained semiconductor layer and the first substrate, wherein removing the first substrate comprises cleaving along the cleave plane. 21. The method of claim 20, wherein forming the cleave plane comprises at least one of implanting ions and forming a porous layer. 22. The method of claim 1, further comprising: removing at least a portion of the first strained semiconductor layer after removing the first substrate. 23. A method for forming a structure, the method comprising: forming a semiconductor layer over a first substrate; mechanically inducing strain in the semiconductor layer to define a first strained semiconductor layer; forming a layer on a backside of the first substrate, the layer comprising at least one of an oxide and a nitride; after forming the layer on the backside of the first substrate, bonding the first strained semiconductor layer directly to an insulator layer disposed on a second substrate; and removing the first substrate from the first strained semiconductor layer, the strained semiconductor layer remaining bonded to the insulator layer. 24. The method of claim 23, wherein forming the semiconductor layer comprises at least one of deposition or epitaxial growth.

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Yuhzoh Tsuda JP; Takayuki Yuasa JP, Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device.
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Howe Roger T. ; Franke Andrea ; King Tsu-Jae, Polycrystalline silicon germanium films for forming micro-electromechanical systems.
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Alexander Yuri Usenko, Process for lift-off of a layer from a substrate.
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Bensahel Daniel,FRX ; Campidelli Yves,FRX ; Hernandez Caroline,FRX ; Rivoire Maurice,FRX, Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively.
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Kondo Shigeki (Hiratsuka JPX) Matsumoto Shigeyuki (Atsugi JPX) Ishizaki Akira (Atsugi JPX) Inoue Shunsuke (Yokohama JPX) Nakamura Yoshio (Atsugi JPX), Process for preparing semiconductor substrate by bonding to a metallic surface.
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Bruel Michel (Veurey FRX) du Port de Poncharra Jean (St. Martin-Le-Vinoux FRX), Process for producing an insulating layer buried in a semiconductor substrate by ion implantation.
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Kakizaki Yasuo,JPX ; Yonehara Takao,JPX ; Sato Nobuhiko,JPX, Process for producing semiconductor article.
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Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
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Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.
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Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
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Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
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Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
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Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
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Fitzgerald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
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Fitzgerald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
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Tsutomu Tezuka JP, Semiconductor device and method of manufacturing the same.
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Shimizu,Akihiro; Ooki,Nagatoshi; Nonaka,Yusuke; Ichinose,Katsuhiko, Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same.
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Wristers, Derick J.; Xiang, Qi; Buller, James F., Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer.
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Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Monroe Donald P. (Berkeley Heights NJ) Silverman Paul J. (Millburn NJ) Xie Ya-Hong (Fl, Semiconductor heterostructure devices with strained semiconductor layers.
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Ihara Masaru (Kawasaki JPX) Jifuku Masayuki (Kawasaki JPX), Semiconductor substrate and method for the preparation of the same.
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Sato Nobuhiko,JPX ; Yonehara Takao,JPX ; Sakaguchi Kiyofumi,JPX, Semiconductor substrate and method of manufacturing the same.
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Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Semiconductor substrate structure.
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Murthy, Anand S.; Doyle, Brian S.; Roberds, Brian E., Semiconductor transistor having a backfilled channel material.
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Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.
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Alexander Yuri Usenko ; William Ned Carr, Separation process for silicon-on-insulator wafer fabrication.
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Capasso Federico (Westfield NJ) Cho Alfred Y. (Summit NJ) Sen Susanta (Scotch Plains NJ), Sequential-quenching resonant-tunneling transistor.
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Sugiura Yoshihisa,JPX ; Iwata Yoshihisa,JPX ; Watanabe Hiroshi,JPX, Shielded bit line sensing scheme for nonvolatile semiconductor memory.
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Schmitz Jurriaan,NLX ; Woerlee Pierre H.,NLX, Si-Ge CMOS semiconductor device.
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Imai Seiji,JPX ; Hiraoka Yoshiko,JPX ; Kurobe Atsushi,JPX ; Sugiyama Naoharu,JPX ; Tezuka Tsutomu,JPX, Si-SiGe semiconductor device and method of fabricating the same.
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Ismail Khalid EzzEldin ; Meyerson Bernard S., Si/SiGe vertical junction field effect transistor.
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Burghartz Joachim N. (Shrub Oak NY) Meyerson Bernard S. (Yorktown Heights NY) Sun Yuan-Chen (Katonah NY), SiGe thin film or SOI MOSFET and method for making the same.
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Soref Richard A. ; Friedman Lionel R., Silicon-based strain-symmetrized GE-SI quantum lasers.
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Huang Feng-Yi, Silicon-germanium bicmos on soi.
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Robinson McDonald ; Westhoff Richard C. ; Hunt Charles E. ; Ling Li, Silicon-germanium-carbon compositions in selective etch processes.
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Judy Xilin An ; Bin Yu, Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation.
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An, Judy Xilin; Yu, Bin, Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation..
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Maszara, Witold P., Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide.
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Ismail Khalid EzzEldin ; Meyerson Bernard S., Single-transistor logic and CMOS inverters.
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Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
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Chu, Jack O.; Ismail, Khaled, Strained Si based layer made by UHV-CVD, and devices therein.
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Chu Jack Oon ; Ismail Khalid EzzEldin, Strained Si/SiGe layers on insulator.
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Chu Jack Oon ; Ismail Khalid EzzEldin, Strained Si/SiGe layers on insulator.
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Clark, William F.; Fried, David M.; Lanzerotti, Louis D.; Nowak, Edward J., Strained fin FETs structure and method.
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Wang, Haihong; Xiang, Qi, Strained silicon MOSFET having silicon source/drain regions and method for its fabrication.
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Xiang, Qi; Paton, Eric N.; Wang, Haihong, Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication.
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Bertin Claude L. (South Burlington VT) DiMaria Donelli J. (Ossining NY) Miyakawa Makoto (Tokyo JPX) Sakaue Yoshinori (Tokyo JPX), Three-dimensional direct-write EEPROM arrays and fabrication methods.
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Bartelink Dirk J., Vertical CMOS digital multi-valued restoring logic device.
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Augusto Carlos Jorge Ramiro Proenca,BEX, Vertical MISFET devices.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain 원문보기

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Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain 원문보기

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