초록 ▼

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are prov

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

대표청구항 ▼

The invention claimed is: 1. A method comprising: receiving data units in the ingress portions of a plurality of port units a control matrix coupled to the port units performing prioritization, allocation, and virtual channel arbitration pursuant to a PCIE specification and setting a sequence in wh

The invention claimed is: 1. A method comprising: receiving data units in the ingress portions of a plurality of port units a control matrix coupled to the port units performing prioritization, allocation, and virtual channel arbitration pursuant to a PCIE specification and setting a sequence in which the data units are sent to egress portions of the port units; transferring data units to the egress portions of the port units in accordance with the sequence set by the control matrix; and outputting data units from the egress portions of the port units, wherein the data units are not reordered after being transferred to the egress portions of the port units. 2. The method of claim 1, wherein the ingress portion of the each port unit includes an input queue, and receiving data units further comprises storing data units in the input queues of the plurality of port units. 3. The method of claim 2, wherein the input queue of each port unit includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue. 4. The method of claim 1, further comprising: the control matrix performing egress flow control and deadlock avoidance pursuant to the PCI Express specification. 5. A switch, comprising: a plurality of port units, each port unit having an ingress portion including an input queue and an egress portion; and a control matrix coupled between the plurality of port units, wherein the control matrix performs prioritization, allocation, and virtual channel arbitration pursuant to a PCI Express specification to determine the sequence in which data units are sent from the ingress portions of the port units to the egress portions of the port units, and wherein data units are not reordered after being sent to the egress portions of the port units. 6. The switch of claim 5 wherein the input queue of each port unit includes a posted transaction queue, a non-posted transaction queue and a completion transaction queue. 7. The switch of claim 5 implemented on a single field programmable gate array. 8. The switch of claim 5 wherein at least two of the port units are coupled with respective devices. 9. The switch of claim 8 wherein each device is selected from the group comprising: a graphics card, a sound card, a network communications unit, a computer peripheral, a computer chip set, and a processor. 10. The switch of claim 5 wherein the control matrix further performs egress flow control and deadlock avoidance pursuant to the PCI Express specification.