IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
UP-0420034
(2006-05-24)
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등록번호 |
US-7594055
(2009-10-20)
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발명자
/ 주소 |
- Gower, Kevin C.
- Maule, Warren E.
- Tremaine, Robert B.
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출원인 / 주소 |
- International Business Machines Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
17 인용 특허 :
205 |
초록
▼
Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signa
Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data. The main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements.
대표청구항
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The invention claimed is: 1. A computer memory system for storing and retrieving data, the system comprising: a memory bus; a main memory controller in communication with the memory bus for generating, receiving, and responding to memory access requests; one or more memory devices characterized by
The invention claimed is: 1. A computer memory system for storing and retrieving data, the system comprising: a memory bus; a main memory controller in communication with the memory bus for generating, receiving, and responding to memory access requests; one or more memory devices characterized by memory device protocols and signaling requirements for command, address, data, voltage and timing operational specifications; and one or more hub devices in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data, wherein the main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements, and the hub devices further comprise device timing and command ordering logic to pre-condition the one or more memory devices in preparation for completing the memory access requests and compile a sequence of memory commands associated with the memory access requests. 2. The system of claim 1 wherein the memory bus is comprised of one or more of electrical signaling and optical signaling. 3. The system of claim 1 wherein at least one of the hub devices is not in communication with any of the memory devices. 4. The system of claim 3 wherein the hub device that is not in communication with any of the memory devices is utilized as a signal repeater for translating between any combination of optical and electrical signals. 5. The system of claim 3 wherein the hub device that is not in communication with any of the memory devices is utilized as a hub for concentrating communication traffic via concatenating separate and independent tags to one or more packets traveling upstream from the hub device that is not in communication with any of the memory devices to the main memory controller, such that resulting packets include information associated with two or more independent operations from one or more separate memory modules. 6. The system of claim 1 wherein one or more of the hub devices add one or more tag bits to the messages for use by the main memory controller in correlating a message from a hub device to one or more of an outstanding memory access request and the hub device. 7. The system of claim 1 wherein the hub devices are in communication with the memory channel in a cascade interconnect or point-to-point manner. 8. The system of claim 1 wherein the main memory controller has a programmable configuration to allow the bus to be configured as a plurality of independent busses, a plurality of busses operating in unison in support of a common message stream, or as a single bus to the hub devices. 9. The system of claim 1 wherein the main memory controller has a programmable configuration for specifying a maximum outstanding messages and data buffering that may be active within the hub device. 10. The system of claim 1 wherein the main memory controller flushes and holds the bus and the hub devices free of messages except control messages for roll-back and recovery, responsive to a detected error condition. 11. The system of claim 1 wherein the main memory controller synchronizes the hub devices for having the memory devices in communication with the hub devices in a consistent state. 12. The system of claim 1 wherein the bus includes an out of order message service and replies with identification tag bits assigned by the main memory controller to received requests and to any associated transmitted bus messages, and the identification tag bit expected on associated received replies from the hub devices. 13. The system of claim 1 wherein one or more of the hub devices include message queues for receiving a plurality of messages before the messages have been serviced. 14. The system of claim 13 wherein the hub devices with the message queues include a programmable priority arbiter for servicing messages in the queues in one or more of an order optimal for a memory device service rate, a power utility and a bus communication efficiency. 15. The system of claim 13 wherein the hub devices with the message queues include a programmable priority arbiter for servicing messages in the queues according to a priority encoded by the main memory controller and included in the messages. 16. The system of claim 1 wherein one or more of the hub devices invalidates a valid message and the hub device is blocked from receiving new messages except for hub device control messages, the blocking in response to a flush control message received from the main memory controller via the bus. 17. The system of claim 16 wherein the hub devices that invalidate a valid message receive and service messages after detecting a specific control message indicating to do so. 18. The system of claim 1 wherein the memory devices in communication with one of the hub devices may be forced to a synchronization point, responsive to a control message received at the hub device from the main memory controller via the bus for having the memory devices in communication with the hub device operate in logical synchrony across a plurality of the hub devices. 19. The system of claim 1 wherein a control reply message may be sent to one of the hub devices, responsive to a specific request to do so, for indicating operation state and conditions to the main memory controller. 20. The system of claim 1, wherein a specific alert state may be encoded into a reply or idle cycle to the hub device, for having the main memory controller responsively poll the hub devices for operation state and conditions. 21. A memory system, the system comprising: at least one main memory controller; a memory bus in communication with the main memory controller; and a memory subsystem including a hub device and in communication with the memory bus for connecting the main memory controller to the memory subsystem, wherein the at least one main memory controller provides operational information to the hub device in a technology-independent format and the hub device comprises device timing and command ordering logic to converts the information into a technology-dependent format that is consistent with command, address, data, voltage and timing operational specifications associated with one or more memory devices attached to the memory subsystem, wherein the device timing and command ordering logic pre-conditions the one or more memory devices in preparation for completing a requested memory operation and compiles a sequence of memory commands associated with the requested memory operation, and information returned to the memory controller includes one or more tag bits to correlate the information to one or more of the requested memory operation, the memory subsystem and the hub device. 22. The system of claim 21 wherein the memory bus includes one or more of a multi-drop bus and a cascade interconnect bus. 23. The system of claim 21 further comprising a second memory bus in communication with the at least one main memory controller and in communication with one or more of the memory subsystem and a second memory subsystem. 24. The system of claim 21 wherein the hub device transmits an indicator to the main memory controller when a command received from the main memory controller has been successfully executed by the hub device. 25. The system of claim 21 wherein a second bus independent of the memory bus is utilized to perform memory system functions. 26. The system of claim 25 wherein the memory system functions performed via the second bus include one or more of initialization and status reporting. 27. A method of storing and retrieving data in a processing system, the method comprising: receiving a technology-independent memory access request from a main memory controller in the processing system, the memory access request received at a hub device in a memory subsystem in the processing system via a memory bus in the processing system; converting the memory access request into a technology-dependent format that is consistent with command, address, data, voltage and timing operational specifications associated with one or more integrated circuit memory devices in the processing system attached to the memory subsystem, wherein the converting the memory access request into the technology-dependent format includes device timing and command ordering logic to pre-condition the one or more integrated circuit memory devices in preparation for completing the memory access request and compile a sequence of memory commands associated with the memory access request; executing the memory access request at the memory subsystem; and if the memory access request requires a response, then generating the response including tag bits for use by the main memory controller in correlating the response to one or more of the memory access request, the memory subsystem, and the hub device. 28. The method of claim 27 wherein the converting the memory access request into a technology-dependent format includes queuing logic to return read data in conjunction with the tag bits at a time unpredicted by a processor in the processing system, and preempting an earlier issued read request without losing the read data returned. 29. A memory subsystem, the memory subsystem comprising: a hub logic device comprising device timing and command ordering logic; and one or more memory devices in communication with the hub logic device, wherein the hub logic device receives commands in a technology-independent format from one or more requestors and converts the commands into a technology-dependent format that is consistent with command, address, data, voltage and timing operational specifications associated with the memory devices, the device timing and command ordering logic pre-conditions the one or more memory devices in preparation for completing the commands and compiles a sequence of memory commands associated with the commands, and if a command requires a response then generating the response including one or more tag bits for correlating the response to one or more of the command and the hub logic device. 30. A memory system, the memory system comprising: at least one main memory controller; a memory subsystem including a hub logic device and one or more memory devices, the hub logic device comprising device timing and command ordering logic to pre-condition the one or more memory devices in preparation for completing requested memory operations and compile a sequence of memory commands associated with the requested memory operations; and a communication bus which connects the at least one main memory controller to the memory subsystem, wherein the at least one main memory controller provides commands including the requested memory operations to the hub logic device in a technology-independent format and the hub logic device converts the commands into a technology-dependent format that is consistent with operational specifications associated with the memory devices, and information returned to the main memory controller from the memory subsystem includes one or more tag bits to correlate the information to one or more of a requested memory operation and the memory subsystem, independent of an order of issuing the requested memory operations. 31. A hub logic device comprising: a memory device interface for converting technology independent memory access requests into technology dependent memory access requests consistent with command, address, data, voltage and timing operational specifications associated with one or more memory devices in communication with the hub logic device; device timing and command ordering logic for pre-conditioning the one or more memory devices in preparation for completing the memory access requests and compiling a sequence of memory commands associated with the memory access requests; and interface logic for receiving the technology independent memory access requests from one or more requestors and if a memory access request requires a response then generating the response including one or more tag bits for correlating the response to the memory access request.
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