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Method and apparatus for generating a phase dependent control signal

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03D-003/24
  • H03D-003/00
  • H03L-007/06
출원번호 UP-0178442 (2008-07-23)
등록번호 US-7602876 (2009-10-28)
발명자 / 주소
  • Harrison, Ronnie M.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Dorsey & Whitney LLP
인용정보 피인용 횟수 : 7  인용 특허 : 276

초록

A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles

대표청구항

The invention claimed is: 1. A phase detector for detecting a phase relationship between a first clock signal and a second clock signal, the phase detector comprising: a first phase detector circuit configured to output a first signal having a first logic level during a time between the rising edge

이 특허에 인용된 특허 (276)

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  191. Conkle Cecil W. (Palo Alto CA), Phase-locked loop timing controller in an integrated circuit memory.
  192. Lesmeister Gary J. (Sunnyvale CA), Phased locked loop to provide precise frequency and phase tracking of two signals.
  193. Landsman Stephen P. (Randallstown MD), Precision phase synchronization of free-running oscillator output signal to reference signal.
  194. Bhullar Gurpreet,CAX ; Allan Graham,CAX, Process, voltage, temperature independent switched delay compensation scheme.
  195. Morzano Christopher K. ; Ingalls Charles L., Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access me.
  196. Koerner Christopher (Longmont CO) Gutierrez ; Jr. Alberto (Fort Collins CO) Pumphrey Edward G. (Colorado Springs CO), Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and volta.
  197. Farago Steven (171 Forest Dr. Mount Kisco NY 10549), Programmable connector.
  198. Cedar Yoram (Sunnyvale CA), Programmable controller.
  199. Yamauchi Shigenori (Kariya JPX) Watanabe Takamoto (Nagoya JPX), Programmable delay line programmable delay circuit and digital controlled oscillator.
  200. Latif Farrukh A. (Malvern PA) Stevens Michael D. (Paoli PA) Moysey John A. (Malvern PA) Shinkarovsky Michael (Harleysville PA) Nguyen Hung (Downingtown PA) Dale Michele Z. (Audubon PA), Programmable multiple I/O interface controller.
  201. Raad George B. (Boise ID), RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line.
  202. Raad George B. (Boise ID), Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line.
  203. Arakawa Hideki (Kanagawa JPX) Narikiyo Takashi (Kanagawa JPX), Random access memory having flash memory.
  204. Furutani Kiyohiro (Itami JPX) Mashiko Koichiro (Itami JPX) Arimoto Kazutami (Itami JPX) Matsumoto Noriaki (Itami JPX) Matsuda Yoshio (Itami JPX), Random access memory with a plurality amplifier groups for reading and writing in normal and test modes.
  205. Harney Kevin (Brooklyn NY) Keith Michael (Washington Crossing PA), Random-access psuedo random number generator.
  206. Leung Wingyu (Cupertino CA) Lee Winston (San Francisco CA) Hsu Fu-Chieh (Saratoga CA), Reduced CMOS-swing clamping circuit for bus lines.
  207. Miller Charles A., Salphasic timing calibration system for an integrated circuit tester.
  208. Farwell William D. (Thousand Oaks CA), Sample and hold flip-flop for CMOS logic.
  209. Tsukada Shyuichi (Tokyo JPX), Selector circuit selecting and outputting voltage applied to one of first and second terminal in response to voltage lev.
  210. Girmay Girmay K. (Inglewood CA), Self calibrating PWM utilizing feedback loop for adjusting duty cycles of output signal.
  211. Crouch Alfred L. (Austin TX) Pressly Matthew D. (Austin TX), Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit str.
  212. Biber Alice I. (Needham MA) Stout Douglas W. (Milton VT), Self-adjusting impedance matching driver.
  213. Peterson LuVerne Ray, Self-calibrating clock circuit employing a continuously variable delay module in a feedback loop.
  214. Partovi Hamid ; Holst John Christian ; Ben-Meir Amos, Self-timed pulse control circuit.
  215. Ohno Yasuhiro (Tokyo JPX) Miyata Manabu (Tokyo JPX), Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed.
  216. Kobayashi Tomohiro (Kanagawa-ken JPX) Fujimoto Yukihiro (Kanagawa-ken JPX), Semiconductor clock signal generation circuit.
  217. Akiyama Noboru (Hitachinaka JPX) Yukutake Seigoh (Kodaira JPX) Ohkuma Sadayuki (Oume JPX) Emori Akihiko (Hitachi JPX) Akioka Takashi (Akishima JPX) Miyaoka Shuichi (Hannou JPX) Nakazato Shinji (Maeba, Semiconductor device.
  218. Aoki Yasushi (Tokyo JPX), Semiconductor integrated circuit device including PLL circuit.
  219. Uchida Toshiya,JPX, Semiconductor integrated circuit for changing pulse width according to frequency of external signal.
  220. Ishibashi Atsuhiko (Hyogo JPX), Semiconductor integrated circuit, method of designing the same and method of manufacturing the same.
  221. Koshikawa Yasuji,JPX, Semiconductor memory device.
  222. Toda Haruki,JPX ; Saito Shozo,JPX ; Tokushige Kaoru,JPX, Semiconductor memory device.
  223. Ichiguchi Tetsuichiro (Hyogo-ken JPX), Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof.
  224. Choi Yun-ho (Incheon KRX), Semiconductor memory device with delay in address predecoder circuit independent from ATD.
  225. Hotta Yasuhiro (Nara JPX), Semiconductor memory device with dual address memory read amplifiers.
  226. Ogura Kiyonori,JPX, Semiconductor memory device with precharge voltage correction circuit.
  227. Fujioka Shinya (Kawasaki JPX) Hatakeyama Atsushi (Kawasaki JPX) Mochizuki Hirohiko (Kawasaki JPX), Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks.
  228. Obara Takashi (Tokyo JPX), Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to all.
  229. Furuhata Takashi (Yokohama JPX) Owashi Hitoaki (Yokohama JPX) Hibi Michio (Osaka JPX), Skew error correction circuit for video signal reproducing apparatus.
  230. I-Teh Sha, Spread spectrum at phase lock loop (PLL) feedback path.
  231. Johnson Mark G. (Los Altos CA), Static high speed comparator.
  232. Hamasaki Toshihiko (Yokohama JPX) Shinohara Yoshiaki (Tokyo JPX) Murota Toshio (Kanagawa JPX) Arihara Ei-ichi (Kawasaki JPX), Switching control circuitry for low noise CMOS inverter.
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  234. Greub Hans-Jurg (Troy NY), Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits.
  235. Hoelzle, Josef, Synchronized, digital sequential circuit.
  236. Kish ; III Joseph (Mesa AZ), Synchronizer for time division multiplexed data.
  237. Mills Duane R. (Folsom CA) Fackenthal Richard (Folsom CA) Rozman Rod (Placerville CA) Rashid Mamun (Fairfield CA), Synchronous address latching for memory arrays.
  238. Yanai Akihiro (Isehara JPX), Synchronous circuit with clock skew compensating function and circuits utilizing same.
  239. Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including a compound delay-locked loop.
  240. Harrison Ronnie M., Synchronous clock generator including a delay-locked loop signal loss detector.
  241. Harrison Ronnie M., Synchronous clock generator including a false lock detector.
  242. Harrison Ronnie M., Synchronous clock generator including a false lock detector.
  243. Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including delay-locked loop.
  244. Wright, Jeffrey P.; Zheng, Hua, Synchronous dynamic random access memory device.
  245. Mullarkey Patrick J., Synchronous memory device having an adjustable data clocking circuit.
  246. Flannagan Stephen T. (Austin TX) Jones Kenneth W. (Austin TX) Kung Roger I. (Austin TX), Synchronous memory having parallel output data paths.
  247. Iwamoto Hisashi,JPX ; Konishi Yasuhiro,JPX, Synchronous semiconductor memory device.
  248. Takasugi Atsushi (Tokyo JPX), Synchronous type semiconductor memory.
  249. Mawhinney Ted N. ; Mundwiler Richard A., System and method for performing non-disruptive diagnostics through a frame relay circuit.
  250. Chengson David P. ; Collins Hansel A. ; Priest Edward C. ; Alvarez Scott W., System and method to reduce jitter in digital delay-locked loops.
  251. Nagae Akihito,JPX, System controller for controlling switching operations of various operation clocks for CPU, DRAM, and the like.
  252. Lipp Robert J. (15881 Rose Ave. Los Gatos CA 95030), System for interconnecting VLSI circuits with transmission line characteristics.
  253. Farmwald Michael ; Horowitz Mark, System having a synchronous memory device.
  254. Malhi Vijay (Milan ITX), Testing a non-volatile memory.
  255. Maruyama Akira (Kawasaki JPX) Yoshida Katsumi (Oyama JPX), Testing apparatus for transmission system.
  256. Gasbarro James A. (Mountain View CA) Horowitz Mark A. (Palo Alto CA), Testing timing parameters of high speed integrated circuit devices.
  257. Vogley Wilbur C. (Missouri City TX), Time skewing arrangement for operating random access memory in synchronism with a data processor.
  258. Pricer W. David (Charlotte VT), Time standard circuit with delay line oscillator.
  259. Goto Masaharu (Hannou JPX), Timing adjustment circuit.
  260. Sato Hideki (Tokyo JPX) Masamura Toshihide (Tokyo JPX), Timing circuit for single line serial data.
  261. Yoshiba Kazumichi,JPX, Timing generator.
  262. Curran Brian W. (Saugerties NY) Blanco Rafael (Burlington VT), Timing signal generator.
  263. Ovens Kevin (Plano TX) Bittlestone Clive (Allen TX) Helmick Bob (Allen TX), Transmission gate circuit.
  264. Procter ; Jr. James A. (Indialantic FL) Otto James C. (Indian Harbour Beach FL), Transponder system and method.
  265. Levine Stephen N. (Chicago IL), Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop.
  266. Mawhinney Ted N. ; Mundwiler Richard A., User-configurable frame relay network.
  267. Hayashi Yokichi (Ohra JPX) Tsukahara Hiroshi (Gyoda JPX) Ochiai Katsumi (Gyoda JPX) Yamada Mashuhiro (Ashikaga JPX) Watanabe Naoyoshi (Gyoda JPX), Variable delay circuit.
  268. Kawai Hiroyuki (Hyogo JPX) Yoshimoto Masahiko (Hyogo JPX), Variable delay circuit for delaying input data.
  269. Hllwegen Josef (Altenbeken DEX), Variable delay unit for data synchronizer using phase-sensitive counter to vary the delay.
  270. Hush Glen (Boise ID) Seibert Mike (Eagle ID) Mailloux Jeff (Boise ID) Thomann Mark R. (Boise ID), Video random access memory device and method implementing independent two WE nibble control.
  271. Casper Stephen L. (Boise ID), Voltage compensating CMOS input buffer.
  272. Casper Stephen L. (Boise ID), Voltage compensating CMOS input buffer.
  273. Sher Joseph C. (Boise ID) Ma Manny K. F. (Boise ID), Voltage compensating CMOS input buffer circuit.
  274. Sauer Donald J. (Allentown NJ), Wide frequency range CMOS relaxation oscillator with variable hysteresis.
  275. Casper Stephen L. (Boise ID) Ong Adrian (Boise ID) Zagar Paul S. (Boise ID), Wordline driver circuit having a directly gated pull-down device.
  276. Flannagan Stephen T. (Austin TX) Chang Ray (Austin TX) Childs Lawrence F. (Austin TX), Write control for a memory using a delay locked loop.

이 특허를 인용한 특허 (7)

  1. Jeong, Chun-Seok; Lee, Jae-Jin; Yoo, Chang-Sik; Park, Jung-June; Seo, Young-Suk, Clock data recovery apparatus.
  2. Kim, Yong Ju; Kwon, Dae Han; Yun, Won Joo; Choi, Hae Rang; Jang, Jae Min, Clock signal duty correction circuit.
  3. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  4. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  5. Kwon, Duk-Min; Song, Ki Whan, Phase change memory.
  6. Kuroki, Koji; Takishita, Ryuji, Semiconductor apparatus.
  7. Kuroki, Koji; Takishita, Ryuji, Semiconductor apparatus.
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