[특허]Adaptable datapath for a digital processing system

QST Holdings, LLC

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Adaptable datapath for a digital processing system

국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-003/00
미국특허분류(USC)	710/004; 710/002; 712/033; 712/201
출원번호	UP-0800577 (2007-05-03)
등록번호	US-7606943 (2009-11-10)
발명자 / 주소	Ramchandran, Amit
출원인 / 주소	QST Holdings, LLC
대리인 / 주소	Nixon Peabody LLP
인용정보	피인용 횟수 : 4 인용 특허 : 382

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The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path....

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What is claimed is: 1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising: a plurality of functional units for performing a digital operation; a plurality of data address generators coupled to the memory bus; a configurable data path configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between and among the plurality of data address generators and the plurality of functional units, the configurable data path including the configured or reconfigured interconnections for the data path configuration; and wherein the plurality of data address generators are coupled between the memory bus and the configurable data path, each of the plurality of data address generators is configurable in response to a second, different configuration information to generate and control memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration. 2. The reconfigurable data path circuit of claim 1, wherein the plurality of data address generators are further configurable or reconfigurable in response to the second, different configuration information to read data of one or more widths from the memory bus consistent with and for the data path configuration. 3. The reconfigurable data path circuit of claim 1, wherein in response to the second configuration information the plurality of data address generators configurably split data received from the memory bus onto the configurable data path. 4. The reconfigurable data path circuit of claim 3, wherein the plurality of data address generators transfer data to the configurable data path for processing by the functional units in parallel. 5. The reconfigurable data path circuit of claim 1, wherein the configurable data path is reconfigured from a first data path configuration having one 16 bit path to a second data path configuration having two 8 bit paths in response to the first configuration information; and each of the plurality of data address generators is configured in response to the second, different configuration information to generate two memory addresses for writing and reading two 8 bit words consistent with and for the second data path configuration. 6. The reconfigurable data path circuit of claim 1, wherein the plurality of data address generators are further configurable in response to the second, different configuration information for transferring data to the memory bus for writing to the memory. 7. The reconfigurable data path circuit of claim 1, wherein the plurality of functional units include a multiplier. 8. The reconfigurable data path circuit of claim 7, wherein the plurality of functional units further include an accumulator, the reconfigurable data path circuit further comprising a direct data path coupling the multiplier and the accumulator. 9. The reconfigurable data path circuit of claim 8, wherein the functional units includes at least one other multiplier, the accumulator adapted to accumulate outputs from the multipliers into a single register, the reconfigurable data path circuit further comprising another direct data path coupling the at least one other multiplier and the accumulator. 10. The reconfigurable data path circuit of claim 9, wherein the plurality of functional units further includes an ALU. 11. The reconfigurable data path circuit of claim 1, further comprising a plurality of register files each configurably interconnected by the configurable data path to the plurality of functional units and to one of the plurality of data address generators. 12. The reconfigurable data path circuit of claim 11, wherein the configurable data path further comprises a reconfigurable interconnection network comprising a plurality of groups of data lines configurably coupled to the plurality of data address generators, the functional units, and the plurality of register files in the configurable data path, wherein each register file of the plurality of register files is coupled to a group of data lines of the plurality of groups of data lines in the configurable data path in a one-to-one correspondence, the plurality of register files adapted for storing data from the respective group of data lines to which the respective ones of the plurality of register files is coupled. 13. The reconfigurable data path circuit of claim 1, wherein the configurable data path further comprises a plurality of groups of data lines coupled to the plurality of data address generators and the plurality of functional units. 14. The reconfigurable data path circuit of claim 13, wherein the configurable data path further comprises a reconfigurable interconnection network comprising the plurality of groups of data lines and being configurable for configuring or reconfiguring the interconnections between and among the plurality of data address generators and the plurality of functional units for the data path configuration. 15. The reconfigurable data path circuit of claim 1, wherein the first and second configuration information each comprises a separate control word. 16. The reconfigurable data path circuit of claim 1, wherein the interconnections of the configurable data path and the plurality of data address generators are configurable in real time. 17. A digital processing system comprising: a memory bus coupled to a memory; and a reconfigurable data path circuit coupled to the memory bus for obtaining data from the memory, the reconfigurable data path circuit comprising: a plurality of functional units for performing a digital operation; and a plurality of data address generators coupled to the memory bus; a configurable data path configurable in response to a first configuration information to provide a data path configuration by configuring or reconfiguring interconnections between and among the plurality of data address generators and the plurality of functional units, the configurable data path including the configured or reconfigured interconnections for the data path configuration; and wherein the plurality of data address generators are coupled between the memory bus and the configurable data path, and each of the plurality of data address generators is configurable in response to a second, different configuration information to generate and control memory addresses from which data is to be read from or written to the memory consistent with and for the data path configuration.

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이 특허를 인용한 특허 피인용횟수: 4

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Adaptable datapath for a digital processing system

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이 특허에 인용된 특허 (382)

이 특허를 인용한 특허 피인용횟수: 4

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Adaptable datapath for a digital processing system

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이 특허에 인용된 특허 (382)

이 특허를 인용한 특허 피인용횟수: 4

IPC 상위 출원인

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IPC 상세정보(version : 201201)

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