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A control system includes a controller configured to provide a drive signal, and a switching device configured to generate an output control signal as a function of the drive signal in an on-state mode of operation. The control system also includes a timing network configured to receive the drive si

A control system includes a controller configured to provide a drive signal, and a switching device configured to generate an output control signal as a function of the drive signal in an on-state mode of operation. The control system also includes a timing network configured to receive the drive signal and output a gated signal to the switching device, wherein the gated signal maintains a relationship with a predetermined threshold during the on-state of operation of the switching device.

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What is claimed is: 1. A control system, comprising: a controller configured to provide a drive signal having a period associated therewith; a switching device configured to generate an output control signal as a function of the drive signal in an on-state mode of operation; and a timing network co

What is claimed is: 1. A control system, comprising: a controller configured to provide a drive signal having a period associated therewith; a switching device configured to generate an output control signal as a function of the drive signal in an on-state mode of operation; and a timing network configured to receive the drive signal and output a gated signal to the switching device, wherein, when the drive signal is asserted, the gated signal maintains a relationship with a predetermined threshold to enable the switching device to alternate between a high-side current state of operation and a low-side current state of operation; and wherein, when the drive signal is continuously de-asserted for more than one period, the gated signal decays to maintain another, different relationship with the predetermined threshold. 2. The control system of claim 1, wherein the relationship comprises the gated signal maintaining a voltage level above the predetermined threshold to enable the switching device to alternate between the high-current state and the low-current state, and where the another, different relationship comprises the gated signal maintaining a voltage level below the predetermined threshold to put the switching device into a sleep-state of operation. 3. A system for driving a motor, comprising: a controlling device configured to provide a drive signal having a drive cycle; a timing network configured to receive the drive signal and generate a gated signal as a function of the drive signal; and a switching device having an operational threshold and configured to receive both the drive signal and the gated signal; wherein, when the drive signal is asserted, the gated signal enables the switching device to deliver a high-side current and a low-side current as a function of the drive signal; and wherein, when the drive signal is continuously de-asserted for more than one drive cycle, the gated signal disables significant current from the switching device; wherein the controlling device is coupled to both the switching device and the timing network via a single primary electrical connection. 4. The system of claim 3, wherein an electrical length of greater than about 0.2 meters separates the controlling device from the timing network and switching device, and wherein the single primary electrical connection spans the electrical length. 5. The system of claim 3, wherein the timing network comprises: a diode; a resistor in parallel with the diode; and a capacitor located such that the gated signal takes more than one period of the drive cycle to drop below the operating threshold of the switching device. 6. A method for driving a motor with a current switching device, comprising: receiving a drive signal at the current switching device, wherein the current switching device drives the motor in response thereto, wherein the drive signal comprises a pulse width modulation signal associated with a period and comprising a first state and a second state during an on-state of the motor; and processing the drive signal with a timing network to generate a gated signal with a decay region, the decay region starting at an initial de-assertion of the drive signal during the on-state of the motor and engineered to cross a predetermined threshold at a predetermined time that is multiple periods removed from the de-assertion to place the current switching device in an off-state during an off-state of the motor. 7. The method of claim 6, further comprising providing the drive signal via a controlling device. 8. The method of claim 7, further comprising coupling the controlling device to both the timing network and the current switching device via a single electrical connection. 9. The method of claim 7, further comprising coupling the controlling device to both the timing network and the current switching device via a single drive signal. 10. The method of claim 7, wherein the step of providing a timing network further comprises: providing a diode; providing a resistor in parallel with the diode; and providing a capacitor located such that the gated signal takes more than one cycle of the drive cycle to drop below an operating threshold of the current switching device. 11. A high current half-bridge, comprising: a controller configured to provide a drive signal having a period associated therewith; a p-channel high-side metal oxide semiconductor field effect transistor for providing a high-side current and voltage; an n-channel low-side metal oxide semiconductor field effect transistor for providing a low-side current and voltage; a driver integrated circuit for selectively control the p-channel high-side metal oxide semiconductor field effect transistor and the n-channel low-side metal oxide semiconductor field effect transistor during an on-state as a function of the drive signal, and a timing network for providing a gated signal to the driver integrated circuit as a function of the drive signal, where the drive signal, when asserted, puts the driver integrated circuit in the on-state, and where the drive signal, when continuously de-asserted for multiple periods, puts the driver integrated circuit in an off-state. 12. The high current half-bridge of claim 11, wherein the p-channel high-side metal oxide semiconductor field effect transistor, the n-channel low-side metal oxide semiconductor field effect transistor, the driver integrated circuit, and timing network are fully integrated in a single integrated circuit. 13. The high current half-bridge of claim 11, wherein the timing network comprises: a diode; a resistor in parallel with the diode; and a capacitor located such that the gated signal takes more than one cycle of the drive cycle to drop below an operating threshold of the half-bridge switching device. 14. The high current half-bridge of claim 13, wherein the timing network comprises a diode having a first node coupled to a primary electrical connection and a second node coupled to a secondary electrical connection; a resistor in parallel with the diode; and a capacitor having a first node coupled to the secondary electrical connection and a second node coupled to ground; and wherein the driver integrated circuit has a first pin coupled to the primary electrical connection and has a second pin coupled to the secondary electrical connection. 15. The high current half-bridge of claim 14, wherein the p-channel high-side metal oxide semiconductor field effect transistor, the n-channel low-side metal oxide semiconductor field effect transistor, the driver integrated circuit, and timing network are fully integrated in a single integrated circuit.