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Configurable integrated circuit with a 4-to-1 multiplexer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G03F-007/38
  • H03K-019/173
  • H01L-025/00
  • H03K-019/20
  • H03K-019/094
출원번호 UP-0371198 (2006-03-08)
등록번호 US-7609085 (2009-11-10)
발명자 / 주소
  • Schmit, Herman
  • Caldwell, Andrew
  • Teig, Steven
출원인 / 주소
  • Tabula, Inc.
대리인 / 주소
    Adeli & Tollen LLP
인용정보 피인용 횟수 : 18  인용 특허 : 123

초록

Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a two-input multiplexer. The second IMUX is also configured as a two-input multiplexer. The LUT is also con

대표청구항

What is claimed is: 1. A four-to-one multiplexer, comprising: a) a first configurable input select multiplexer comprising more than two data inputs, a first set of selection inputs, and a second set of selection inputs, wherein said first configurable input select multiplexer is configured to opera

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이 특허를 인용한 특허 (18)

  1. Parlour, David B.; Janneck, Jorn W.; Miller, Ian D., Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit.
  2. Young, Steven P.; Gaide, Brian C., Bus-based logic blocks for self-timed integrated circuits.
  3. Young, Steven P., Bus-based logic blocks with optional constant input.
  4. Young, Steven P., Cascading input structure for logic blocks in integrated circuits.
  5. Young, Steven P.; Gaide, Brian C., Circuits for sharing self-timed logic.
  6. Young, Steven P.; Gaide, Brian C., Circuits for shifting bussed data.
  7. Young, Steven P.; Gaide, Brian C., Compute-centric architecture for integrated circuits.
  8. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor.
  9. Zhang, Wei; Jha, Niraj K.; Shang, Li, Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore.
  10. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.
  11. Young, Steven P.; Gaide, Brian C., Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same.
  12. Young, Steven P., Multiplier circuits with optional shift function.
  13. Young, Steven P.; Gaide, Brian C., Signed multiplier circuit utilizing a uniform array of logic blocks.
  14. Schmit, Herman; Caldwell, Andrew; Hutchings, Brad; Redgrave, Jason; Teig, Steven, System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture.
  15. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.
  16. Schmit, Herman; Teig, Steven; Hutchings, Brad, System and method for providing more logical memory ports than physical memory ports.
  17. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power usage.
  18. Schmit, Herman; Pugh, Daniel J.; Teig, Steven, System and method of providing a memory hierarchy.
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