초록 ▼

An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a

An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.

대표청구항 ▼

What is claimed: 1. A processor node configured to operate within an array of processor nodes in a multiprocessor system, the processor node comprising: a processor configured to execute instructions and including a processor network switch; a first input/output interface configured to process comm

What is claimed: 1. A processor node configured to operate within an array of processor nodes in a multiprocessor system, the processor node comprising: a processor configured to execute instructions and including a processor network switch; a first input/output interface configured to process communications with an external device outside the array of processor nodes; a first inter-processor interface configured to process communications with a second processor node within the array of processor nodes; and a selection circuit coupled to the first input/output interface and the first inter-processor interface and further coupled to one of the external device and the second processor node, the selection circuit configured to select between the first input/output interface and the first inter-processor interface, based on whether the selection circuit is further coupled to the external device or to the second processor node, wherein the processor, the first input/output interface, the first inter-processor interface, and the selection circuit are included within the processor node. 2. The processor node of claim 1 further comprising: a second input/output interface configured to process communications with a second external device outside the array of processor nodes; a second inter-processor interface configured to process communications with a third processor node within the array of processor nodes; and a second selection circuit coupled to the second input/output interface and the second inter-processor interface and further coupled to one of the second external device and the third processor node, the selection circuit configured to select between the second input/output interface and the second inter-processor interface, based on whether the second selection circuit is further coupled to the second external device or to the third processor node, wherein the second input/output interface, the second inter-processor interface, and the second selection circuit are included within the processor node. 3. The processor node of claim 1 wherein there are four input/output interfaces each coupled to one of four selection circuits and four inter-processor interfaces, each coupled to one of the four selection circuits. 4. The processor node of claim 1 wherein the processor comprises a processing element configured to execute a standard set of instructions and a software extensible device configured to execute an instruction not included in the set of standard instructions in the processing element, wherein the additional instruction can be programmed by software. 5. The processor node of claim 1 wherein the selection circuit comprises a multiplexer/demultiplexer. 6. The processor node of claim 1 wherein the first input/output interface comprises a peripheral component interconnect interface. 7. The processor node of claim 1 wherein a component of the first input/output interface is a double data rate synchronous DRAM interface, a universal asynchronous receiver/transmitter interface, or an Ethernet interface. 8. The processor node of claim 1 wherein the processor node is disposed in a first integrated circuit and the second processor node is disposed in a second integrated circuit, and the first inter-processor interface is configured to handle off-chip communications with the second processor node. 9. The processor node of claim 8 wherein the selection circuit is configured to select between the first input/output interface and the first inter-processor interface based on a signal on a pin on the first integrated circuit. 10. The processor node of claim 1 wherein the first inter-processor interface is configured to perform buffering. 11. The processor node of claim 1 wherein the first inter-processor interface is configured to handle latency problems. 12. The processor node of claim 1 wherein the selection circuit is configured to receive a selection signal and select between the first input/output interface and the first inter-processor interface based on the selection signal. 13. The processor node of claim 12 wherein the selection circuit is configured to receive the selection signal from a processor control software. 14. The processor node of claim 12 wherein the selection circuit is configured to receive the selection signal during a packaging process. 15. The processor node of claim 1 wherein the selection circuit is configured to both send and receive data. 16. The processor node of claim 1 wherein the selection circuit is configured to receive data on both a rising edge and a falling edge of a clock signal. 17. The processor node of claim 1 wherein the selection circuit is configured to receive input signals of different voltages. 18. The processor node of claim 1 wherein the selection circuit is configured to transmit output signals of different voltages. 19. The processor node of claim 1 further comprising a third processor node, the third processor node comprising: a second input/output interface configured to process communications with a second external device outside the array of processor nodes; a second inter-processor interface configured to process communications with a fourth processor node within the array of processor nodes; and a second selection circuit coupled to the second input/output interface and the second inter-processor interface and further coupled to one of the second external device and the fourth processor node, the selection circuit configured to select between the second input/output interface and the second inter-processor interface, based on whether the selection circuit is further coupled to the second external device or to the fourth processor node. 20. The processor node of claim 1 wherein the first and second processor nodes are disposed in the same integrated circuit. 21. The processor node of claim 1 wherein the second processor node comprises: a second input/output interface configured to process communications with a second external device outside the array of processor nodes; a second inter-processor interface configured to process communications with the processor node; and a second selection circuit coupled to the second input/output interface and the second inter-processor interface and further coupled to the processor node, the selection circuit configured to select the second inter-processor interface. 22. A method of operating a selection circuit in a processor node within an array of processor nodes, the processor node including a processor, a processor network switch, an input/output interface, and an inter-processor interface, the selection circuit coupled to the input/output interface and the inter-processor interface, the method comprising: detecting that the selection circuit is coupled to one of an external device outside the array of processor nodes and a second processor node within the array of processor nodes; receiving at the selection circuit a selection signal based on the detection; selecting between the input/output interface and the inter-processor interface based on the selection signal, using the selection circuit; communicating standard input/output communications via the input/output interface between the processor and the external device based on a selection of the input/output interface; and communicating inter-processor communications via the inter-processor interface between the processor and the second processor node based on a selection of the inter-processor interface. 23. The method of claim 22 wherein the processor comprises a processing element configured to execute a set of standard instructions and a software extensible device configured to execute an instruction not included in the set of standard instructions in the processing element, wherein the additional instruction can be programmed by software. 24. The method of claim 22 wherein the selection circuit is a multiplexer/demultiplexer. 25. The method of claim 22 wherein the standard input/output communications are conducted in a peripheral component interconnect protocol. 26. The method of claim 22 wherein the standard input/output communications are conducted in a double data rate synchronous DRAM protocol, a universal asynchronous receiver/transmitter protocol. or an Ethernet protocol. 27. The method of claim 22 wherein the inter-processor communications comprise off-chip communications with the second processor. 28. The method of claim 22 wherein processing the inter-processor communications further comprises performing buffering. 29. The method of claim 22 wherein processing the inter-processor communications further comprises handling latency problems. 30. The method of claim 22 wherein the selection signal is received from a processor control software. 31. The method of claim 22 wherein the selection signal is received during a packaging process. 32. The method of claim 22 wherein selecting between the input/output interface and the inter-processor interface is based on a pin on the integrated circuit. 33. The method of claim 22 wherein selecting between the input/output interface and the inter-processor interface is further based on a topological relationship between the processor and a neighboring device, wherein the neighboring device is the second processor node or the external device. 34. The method of claim 22 wherein the inter-processor communications flow from the processor to the inter-processor interface and then to the selection circuit. 35. The method of claim 22 wherein the standard input/output communications flow from the selection circuit to the input/output interface and then to the processor. 36. A method of operating an array of processor nodes, a first processor node of the array including a processor, a processor network switch, a first selection circuit coupled to a first input/output interface and to a first inter-processor interface, and a second selection circuit coupled to a second input/output interface and to a second inter-processor interface the method comprising: selecting the first input/output interface using the first selection circuit; selecting the second selection circuit using the second inter-processor interface; receiving and transmitting standard input/output communications to a device outside the array of processor nodes using the first input/output interface; and processing inter-processor communications to a second processor node within the array of processor nodes using the second inter-processor interface. 37. The method of claim 36 wherein the first selection circuit is coupled to a conductor, the conductor configured for conveying standard input/output communications from the first input/output interface and for conveying inter-processor communications from the first inter-processor interface.