초록 ▼

A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a user request unit which issues a request for performing a data operation on a flash memory using a prede

A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a user request unit which issues a request for performing a data operation on a flash memory using a predetermined logical address, a conversion unit which converts the logical address into a physical address, and a control unit which performs the data operation on the physical address and writes inverted data obtained by inverting error correction code (ECC) corresponding to data used in the data operation to a region indicating whether the ECC is erroneous.

대표청구항 ▼

What is claimed is: 1. A data processing apparatus for a flash memory comprising: a user request unit which issues a request for performing a data operation on a flash memory using a logical address; a conversion unit which converts the logical address into a physical address; and a control unit wh

What is claimed is: 1. A data processing apparatus for a flash memory comprising: a user request unit which issues a request for performing a data operation on a flash memory using a logical address; a conversion unit which converts the logical address into a physical address; and a control unit which performs the data operation on the physical address and writes inverted data to an inverted data region of the flash memory, the inverted data used to indicate whether an extracted ECC is erroneous, wherein, before performing the data operation, the control unit obtains the inverted data and loads the inverted data into a buffer by inverting generated error correction code (ECC) loaded in the buffer, the generated ECC corresponding to data loaded in the buffer which is to be used in the data operation, and wherein, while performing the data operation, the control unit writes the inverted data from the buffer to the inverted data region of the flash memory, and writes the generated ECC from the buffer to an ECC region of the flash memory to be extracted from the ECC region as the extracted ECC, the inverted data and the extracted ECC being mutually exclusive of each other. 2. The data processing apparatus of claim 1, wherein the inverted data is inverse relative to the generated ECC, which is generated from the data loaded into the buffer to be used in the data operation, and the extracted ECC corresponds to the generated ECC, the extracted ECC being written to the ECC region of the flash memory. 3. A data processing apparatus for a flash memory comprising: an extraction unit which extracts from memory regions of the flash memory error correction code (ECC) and inverted data, the inverted data being obtained before a data operation requested by a user is performed by inverting generated ECC loaded in a buffer, the generated ECC generated from data loaded into the buffer to be used in the data operation not yet performed, the extracted ECC and the extracted inverted data each corresponding to data located at a logical address; and a control unit which determines whether the extracted ECC is erroneous and a number of erroneous bits included in the extracted ECC with reference to a relationship between the extracted ECC and the extracted inverted data, wherein the extracted inverted data and the extracted ECC are mutually exclusive of each other. 4. The data processing apparatus of claim 3, wherein the extracted ECC corresponds to the generated ECC, the extracted ECC being written to an ECC region of the flash memory and the extracted inverted data being written to an inverted data region of the flash memory. 5. The data processing apparatus of claim 4, wherein the control unit determines that the extracted ECC is valid if the extracted ECC matches ECC obtained by inverting the extracted inverted data. 6. The data processing apparatus of claim 5, wherein, if the number of erroneous bits included in the extracted ECC is not smaller than a predefined number, the control unit determines that the data located at the logical address, the extracted ECC, and the extracted inverted data are invalid. 7. The data processing apparatus of claim 6, wherein, if the number of erroneous bits included in the extracted ECC is smaller than the predefined number, the control unit generates another ECC based on the data located at the logical address, compares the other generated ECC with the extracted ECC, and determines whether the data located at the logical address is erroneous based on a comparison result. 8. A data processing method for a flash memory comprising: issuing a request for performing a data operation on a flash memory using a logical address; converting the logical address into a physical address; before performing the data operation, obtaining inverted data by inverting a generated error correction code (ECC) loaded in a buffer corresponding to data loaded in the buffer which is to be used in the data operation, and loading the inverted data into the buffer; performing the data operation on the physical address, writing inverted data loaded in the buffer and obtained by inverting the generated error correction code (ECC) corresponding to data used in the data operation to an inverted data region of the flash memory, and writing the generated ECC from the buffer to an ECC region of the flash memory to be extracted from the ECC region as an extracted ECC, the inverted data used to indicate whether an-the extracted ECC stored in the ECC region of the flash memory is erroneous, wherein the inverted data and the extracted ECC are mutually exclusive of each other. 9. The data processing method of claim 8, wherein the inverted data is inverse relative to the generated ECC, which is generated from the data loaded into the buffer to be used in the data operation, and the extracted ECC corresponds to the generated ECC, the extracted ECC being written to the ECC region of the flash memory. 10. A data processing method for a flash memory comprising: extracting error correction code (ECC) and inverted data, the inverted data being obtained by inverting generated ECC loaded in a buffer and generated from data loaded into the buffer to be used in the data operation not yet performed, the extracted ECC and the extracted inverted data each corresponding to data located at a logical address; and determining whether the extracted ECC is erroneous and a number of erroneous bits included in the extracted ECC with reference to a relationship between the extracted ECC and the extracted inverted data, wherein the extracted inverted data and the extracted ECC are mutually exclusive of each other. 11. The data processing method of claim 10, wherein the extracted ECC corresponds to the generated ECC, the extracted ECC being written to an ECC region of the flash memory and the extracted inverted data being written to an inverted data region of the flash memory. 12. The data processing method of claim 11, wherein the determining of whether the extracted ECC is erroneous comprises: inverting the extracted inverted data; and determining that the extracted ECC is valid if the inverted result matches the extracted ECC. 13. The data processing method of claim 12, wherein the determining of whether the extracted ECC is erroneous comprises determining that the data located at the logical address, the extracted ECC, and the extracted inverted data are invalid if the number of erroneous bits included in the extracted ECC is not smaller than a predefined number. 14. The data processing method of claim 13, wherein the determining of whether the extracted ECC is erroneous comprises: if the number of erroneous bits included in the extracted ECC is smaller than the predefined number, generating another ECC based on the data located at the logical address; comparing the generated other ECC with the extracted ECC; and determining whether the data located at the logical address is erroneous based on a result of the comparing. 15. A data processing apparatus of a flash memory comprising: a user request unit which issues a request for performing a data operation on a flash memory using a logical address; a conversion unit which converts the logical address into a physical address; a control unit which, before performing the data operation, generates error correction code (ECC) corresponding to data loaded in a buffer to be used in the data operation not vet performed and loads the generated ECC into the buffer, generates inverted data by inverting the generated ECC loaded into the buffer, performs the data operation on the physical address using the data, and writes the inverted data and the generated ECC to the flash memory while performing the data operation; and an extraction unit which extracts the ECC and the inverted data written to the flash memory; wherein the control unit determines whether the extracted FCC is erroneous and a number of erroneous bits included in the extracted ECC with reference to a relationship between the extracted ECC and the extracted inverted data, and the extracted inverted data and the extracted ECC are mutually exclusive of each other. 16. The data processing apparatus of claim 15, wherein the extracted ECC corresponds to the generated ECC, the extracted ECC being written to an ECC region of the flash memory and the extracted inverted data being written to an inverted data region of the flash memory. 17. The data processing apparatus of claim 16, wherein the control unit determines that the extracted ECC is valid if the extracted ECC matches ECC obtained by inverting the extracted inverted data. 18. The data processing apparatus of claim 17, wherein, if the number of erroneous bits included in the extracted ECC is not smaller than a predefined number, the control unit determines that the data located at the logical address, the extracted ECC, and the extracted inverted data are invalid. 19. The data processing apparatus of claim 18, wherein, if the number of erroneous bits included in the extracted ECC is smaller than the predefined number, the control unit generates another ECC based on the data located at the logical address, compares the other generated ECC with the extracted ECC, and determines whether the data located at the logical address is erroneous based on a comparison result. 20. The data processing apparatus of claim 7, wherein the predefined number is two.