초록 ▼

Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one

Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine.

대표청구항 ▼

What is claimed is: 1. A system for providing individualized design for embedded systems using an adaptive computing engine, the system comprising: a plurality of heterogeneous processing nodes, each one of the heterogeneous processing nodes including an interface that supports a definition of the

What is claimed is: 1. A system for providing individualized design for embedded systems using an adaptive computing engine, the system comprising: a plurality of heterogeneous processing nodes, each one of the heterogeneous processing nodes including an interface that supports a definition of the processing performed by the adaptive computing engine through customization of elements in each of the heterogeneous processing nodes, wherein each of the heterogeneous processing nodes comprises a plurality of reconfigurable matrices, and each of the matrices includes a different mix of fixed and configurable application specific integrated circuits; a controller for separately configuring each one of the heterogeneous processing nodes according to individualized design needs of the adaptive computing engine thereby providing a desired embedded function; a matrix interconnection network for communication between each of the heterogeneous processing nodes and a controller and carrying data capable of configuring and reconfiguring the plurality of heterogeneous processing nodes to execute different functions in the heterogeneous processing nodes, the matrix interconnection network supporting plural services including direct memory access services and read/write services between the heterogeneous processing nodes and a host processor; and a network root configured to communicate with a first network and a second network, wherein a first set of the plurality of heterogeneous processing nodes is configured as a first group that is configured to execute a plurality of functional nodes and that communicates using the first network, and wherein a second set of the plurality of heterogeneous processing nodes is configured as a second group that is configured to execute a plurality of functional nodes different than the functional nodes executed by the first group and that communicates using the second network, the network root providing communication between each of the nodes of the first and second groups and a single common system interface, a bulk RAM, a common memory interface, and a network output interface. 2. The system of claim 1 wherein the interface further comprises a node wrapper unit interfacing with a node memory unit and a node execution unit. 3. The system of claim 2 wherein the interface supports supplementation through replacement of the node execution unit with a customized node execution unit in one or more of the plurality of heterogeneous processing nodes. 4. The system of claim 3 wherein the node wrapper unit further interfaces with the matrix interconnection network. 5. The system of claim 2, wherein the node execution unit is configured to be in an idle state when a node enabled signal is not asserted by the node wrapper or when the node enabled signal is asserted by the node wrapper and an execution unit run signal is not asserted by the node wrapper. 6. The system of claim 5, wherein the node execution unit is configured to perform initialization, execution, and generate an acknowledge message that is output to the node wrapper when the node execution unit transitions from the idle state to a run state. 7. The system of claim 6, wherein the acknowledge message includes a test indication. 8. The system of claim 6, wherein, after processing the acknowledge message, the node wrapper is configured to assert, for one clock period, an execution unit continue signal to the node execution unit to cause the node execution unit to resume execution of a task. 9. The system of claim 8, wherein the node wrapper is configured to asserted the execution unit continue signal when a go bit associated with the task is asserted, buffers associated with the task are available, and a ready-to-run FIFO is empty. 10. The system of claim 6, wherein, after processing the acknowledge message, the node wrapper is configured to assert, for one clock period, an execution unit teardown signal to the node execution unit to cause the node execution unit to complete teardown of a task. 11. The system of claim 10, wherein the node execution unit is configured to assert an execution unit done signal to the node wrapper when teardown of the task is completed. 12. The system of claim 11, wherein the node wrapper is configured to de-assert the execution unit run signal when the node wrapper the execution unit done signal is asserted. 13. The system of claim 2, wherein the execution unit is configured to trigger a message from the node wrapper to a K-node that is coupled to the network root by asserting a message request signal to the node wrapper and write information identifying a trigger condition in a module parameter list in the K-node. 14. The system of claim 1, wherein the first network is a first homogeneous network, the second network is a second homogeneous network, and the network root is configured for communication between the first homogeneous network to the second homogeneous network. 15. The system of claim 1, wherein the plurality of heterogeneous processing nodes comprises: a first one of the plurality of heterogeneous processing nodes configured to perform a first function according to the individualized design needs; a second one of the plurality of heterogeneous processing nodes configured to perform a second function according to the individualized design needs that is different than the first function; and additional heterogeneous processing nodes within the plurality of heterogeneous processing nodes that are each configured to perform a different function than any of the other heterogeneous processing nodes. 16. The system of claim 1, wherein the controller includes a kernel controller that is configured to provide a first control functionality and a matrix controller that is configured to provide a second control functionality. 17. A system for providing individualized design for embedded systems using an adaptive computing engine, the system comprising: an infrastructure means to support a plurality of heterogeneous processing nodes as the adaptive engine, the infrastructure including: the heterogeneous processing nodes, each of the heterogeneous processing nodes comprising a plurality of reconfigurable matrices, and each of the matrices including a different mix of fixed and configurable application specific integrated circuits; a controller for separately configuring each one of the heterogeneous processing nodes according to individualized design needs of the adaptive computing engine thereby providing a desired embedded function; and a single set of wires defining a matrix interconnection network for communication between each of the heterogeneous processing nodes and a controller and carrying data capable of configuring and reconfiguring the plurality of heterogeneous processing nodes to execute different functions in the heterogeneous processing nodes, the matrix interconnection network supporting plural services including direct memory access services and read/write services between the heterogeneous processing nodes and a host processor; means for utilizing the infrastructure to customize a first one of the heterogeneous processing nodes according to the individualized design needs to provide the desired embedded system; means for utilizing the infrastructure to customize a second one of the heterogeneous processing nodes according to the individualized design needs to provide the desired embedded system, wherein the second one of the heterogeneous processing nodes is configured to perform a different function than the first one of the heterogeneous processing nodes; means for utilizing the infrastructure to customize any remaining heterogeneous processing nodes according to the individualized design needs to provide the desired embedded system, wherein each one of the remaining heterogeneous processing nodes is configured to perform a different function than any of the other heterogeneous processing nodes; and a network root configured to communicate with a first network and a second network, wherein a first set of the heterogeneous processing nodes is configured as a first group that is configured to execute a plurality of functional nodes and that communicates using the first network, and a second set of the heterogeneous processing nodes is configured as a second group that is configured to execute a plurality of functional nodes different than the functional nodes executed by the first group and that communicates using the second network, the network root providing communication between each of the nodes of the first and second groups and a single common system interface, a bulk RAM, a common memory interface, and a network output interface. 18. The system of claim 17 wherein the infrastructure means further comprises a predetermined set of interfaces within and among the plurality of heterogeneous nodes. 19. The system of claim 18 wherein the interfaces within each one of the heterogeneous processing nodes further comprise interfaces between a memory unit, a node wrapper unit, and an execution unit. 20. The system of claim 19 wherein the means for utilizing the infrastructure further comprises a customized execution unit that replaces the execution unit and interfaces with the memory unit and node wrapper unit within at least one of the heterogeneous processing nodes.