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Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/82
  • G06F-015/76
출원번호 UP-0733064 (2007-04-09)
등록번호 US-7620800 (2009-11-27)
발명자 / 주소
  • Huppenthal, Jon M.
  • Caliga, David E.
출원인 / 주소
  • SRC Computers, Inc.
대리인 / 주소
    Martensen, Michael C.
인용정보 피인용 횟수 : 29  인용 특허 : 35

초록

Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, c

대표청구항

What is claimed is: 1. A method for data processing in a reconfigurable computing system, the reconfigurable computing system comprising at least one reconfigurable processor, the reconfigurable processor comprising a plurality of functional units, said method comprising: transforming an algorithm

이 특허에 인용된 특허 (35)

  1. Skaletzky Gil,ILX ; Freizeit Amir,ILX ; Sperling Erez,ILX ; Harlap Michal,ILX ; Steiner Moshe,ILX, Apparatus for and method of reducing the memory bandwidth requirements of a systolic array.
  2. Shail Aditya Gupta ; B. Ramakrishna Rau ; Vinod K. Kathail ; Michael S. Schlansker, Auto design of VLIW processors.
  3. Casselman Steven M., Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed.
  4. Casselman Steven M., Computer with programmable arrays which are reconfigurable in response to instructions to be executed.
  5. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.
  6. Woodfill John Iselin ; Baker Henry Harlyn ; Herzen Brian Von ; Alkire Robert Dale, Data processing system and method.
  7. Cloutier Jocelyn, FPGA-based processor.
  8. Leeland Steven B. (Phoenix AZ), Floating-point systolic array including serial processors.
  9. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  10. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.
  11. Thomas C. Douglass, Method and apparatus for customization of information content provided to a requestor over a network using demographic information yet the user remains anonymous to the server.
  12. Helbig ; Sr. Walter A, Method and apparatus for enhancing computer system security.
  13. Burke, David, Method and apparatus for executing standard functions in a computer system using a field programmable gate array.
  14. Fandrich Mickey L. (Placerville CA) Durante Richard J. (Citrus Heights CA) Underwood Keith F. (Orangevale CA) Rozman Rodney R. (Placerville CA), Method and apparatus for execution of operations in a flash memory array.
  15. Fong Anthony S. (Southboro MA), Method and apparatus for floating point operations.
  16. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
  17. Benner Robert E. (Albuquerque NM) Gustafson John L. (Albuquerque NM) Montry Gary R. (Albuquerque NM), Method for simultaneous overlapped communications between neighboring processors in a multiple.
  18. Huppenthal Jon M. ; Leskar Paul A., Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem.
  19. Grunewald Paul ; Stelter Wesley H. ; Ding Jiangang, PCI-compliant interrupt steering architecture.
  20. Chang Chi-Yung (Torrance CA) Fang Wai-Chi (San Marino CA) Curlander John C. (Pasadena CA), Pipeline synthetic aperture radar data compression utilizing systolic binary tree-searched architecture for vector quant.
  21. Tan Charles M. C., Programmable gate array configuration memory which allows sharing with user memory.
  22. Lytle Craig S. (Mountain View CA) Faria Donald F. (San Jose CA), Programmable logic array integrated circuit incorporating a first-in first-out memory.
  23. Gorin Allen L. (Fair Lawn NJ) Makofsky Patrick A. (Randolph NJ) Morton Nancy (Dover NJ) Oliver Neal C. (Madison NJ) Shively Richard R. (Convent Station NJ) Stanziola Christopher A. (Hyde Park NY), Reconfigurable signal processor.
  24. Shido Tatsuya (Kawasaki JPX) Kawamura Kaoru (Yokohama JPX) Umeda Masanobu (Yokohama JPX) Shibuya Toshiyuki (Inagi JPX) Miwatari Hideki (Yokohama JPX), SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respectiv.
  25. Sgro Joseph A. ; Stanton Paul C., Scalable multi-processor architecture for SIMD and MIMD operations.
  26. Pechanek Gerald George (Endwell NY) Vassiliadis Stamatis (Vestal NY) Delgado-Frias Jose Guadalupe (Endwell NY), Scalable parallel group partitioned diagonal-fold switching tree computing apparatus.
  27. Panchul Yuri V. ; Soderman Donald A. ; Coleman Denis R., System for converting hardware designs in high-level programming language to hardware implementations.
  28. De Oliveira Kastrup Pereira, Bernardo; Bink, Adrianus J.; Hoogerbrugge, Jan, System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time.
  29. McWhirter John G. (Malvern Wells GB2), Systolic array.
  30. Khan Emdadur R. (San Jose CA), Systolic array for multidimensional matrix computations.
  31. Means Robert W. (Rancho Santa Fe CA) Sklar Horace J. (Escondido CA), Systolic array image processing system and method.
  32. Helbig ; Sr. Walter A. (Medford Lakes NJ), Systolic array processing apparatus.
  33. Gai Weixin,CNX ; Chen Hongyi,CNX, Systolic linear-array modular multiplier with pipeline processing elements.
  34. Casselman Steven, Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs.
  35. Stewart Gordon Gregory, Web server mechanism for processing function calls for dynamic data queries in a web page.

이 특허를 인용한 특허 (29)

  1. Lu, Pengbo; Beckner, Bret L., Adaptive Newton's method for reservoir simulation.
  2. Kwon, Ki-Seok; Kim, Suk-Jin; Mahlke, Scott; Park, Yong-Jun, Compiling apparatus and method of a multicore device.
  3. Ghayour, Kaveh; Bi, Linfeng; Wu, Xiaohui, Fault removal in geological models.
  4. Lu, Pengbo; Beckner, Bret L., Flexible and adaptive formulations for complex reservoir simulations.
  5. Mishev, Ilya D.; Dubois, Olivier; Jiang, Lijian, Method and system for finite volume simulation of flow.
  6. Maliassov, Serguei, Method and system for parallel simulation models.
  7. Usadi, Adam; Li, Dachang; Parashkevov, Rossen; Wu, Xiaohui; Yang, Yahan, Method and system for reservoir modeling.
  8. Suzuki, Satomi, Method for multiphase flow upscaling.
  9. Kural, Deniz, Methods and systems for aligning sequences.
  10. Kural, Deniz, Methods and systems for detecting sequence variants.
  11. Kural, Deniz, Methods and systems for detecting sequence variants.
  12. Kural, Deniz, Methods and systems for detecting sequence variants.
  13. Kural, Deniz, Methods and systems for genotyping genetic samples.
  14. Kural, Deniz, Methods and systems for identifying disease-induced mutations.
  15. Usadi, Adam; Li, Dachang; Parashkevov, Rossen; Terekhov, Sergey A.; Wu, Xiaohui; Yang, Yahan, Methods and systems for machine-learning based simulation of flow.
  16. Usadi, Adam; Li, Dachang; Parashkevov, Rossen; Terekhov, Sergey A.; Wu, Xiaohui; Yang, Yahan, Methods and systems for machine—learning based simulation of flow.
  17. Haugen, Kjetil B., Optimized matrix and vector operations in instruction limited algorithms that perform EOS calculations.
  18. McGarry, Patrick F.; Sorber, David B.; Bresnan, Timothy P.; Huo, Andrew; Harris, Robert M.; Agrawal, Varun K., Storage management systems and methods.
  19. Tewalt, Timothy J., System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers.
  20. Tewalt, Timothy J., System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem.
  21. Kural, Deniz, Systems and methods for analyzing sequence data.
  22. Semenyuk, Vladimir, Systems and methods for genomic pattern analysis.
  23. Brown, Richard, Systems and methods for genotyping with graph reference.
  24. McGarry, Patrick F.; Sorber, David B.; Bresnan, Timothy P.; Huo, Andrew, Systems and methods for managing execution of specialized processors.
  25. McGarry, Patrick F.; Sorber, David B.; Bresnan, Timothy P.; Huo, Andrew; Agrawal, Varun K.; Stupar, Brian R.; Griffin, Christopher M.; Barthelemy, Jeremy L.; Harris, Robert M.; Gantz, Paul C., Systems and methods for performing primitive tasks using specialized processors.
  26. Tijanic, Nebojsa; Stojanovic, Luka; Cohadarevic, Damir; Ivkovic, Sinisa, Systems and methods for smart tools in sequence pipelines.
  27. Tijanic, Nebojsa; Stojanovic, Luka; Cohadarevic, Damir; Ivkovic, Sinisa, Systems and methods for smart tools in sequence pipelines.
  28. Kural, Deniz; Meyvis, Nathan, Systems and methods for using paired-end data in directed acyclic structure.
  29. Yang, Yahan; Bi, Linfeng; Guo, Weidong; Parashkevov, Rossen; Wu, Xiaohui, Variable discretization method for flow simulation on complex geological models.
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