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A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat o

A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibility in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions. The use of RFI in a processor containing multiple heterogeneous execution units which operate in parallel, such as VLIW or iVLIW processors, allows for efficient pipelining of algorithms across multiple execution units while minimizing the number of VLIW instructions required.

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We claim: 1. A data processor with register file indexing comprising: an instruction sequencer and N execution units capable of executing up to N instructions in parallel; a plurality of register files with registers which contain data operands read and written by the N execution units, each regis

We claim: 1. A data processor with register file indexing comprising: an instruction sequencer and N execution units capable of executing up to N instructions in parallel; a plurality of register files with registers which contain data operands read and written by the N execution units, each register file having read ports to and write ports from the N execution units; and read and write ports associated with each execution unit which have associated control circuitry and register file index (RFI) control registers which control the selection of a first addressing approach and a second indirect addressing approach and allow registers to be addressed using both a the first addressing approach in which fields of an instruction word made available to a particular execution unit directly specify addresses, and a the second indirect addressing approach in which the contents of register file index look ahead registers are utilized in specifying the addresses. 2. The apparatus of claim 1 wherein said processor is a VLIW processor. 3. The apparatus of claim 1 wherein said processor is an iVLIW processor. 4. The apparatus of claim 1 wherein said processor is one of a plurality of similarly configured processors in a ManArray architecture. 5. The apparatus of claim 1 further comprising a control mechanism whereby an instruction may optionally use one or more RFI look ahead registers to supply the address for its register file operands. 6. The apparatus of claim 1 further comprising a control mechanism whereby the RFI look ahead register may be optionally updated automatically after each use by adding or subtracting a constant from its current register address thereby selecting a different register for its next use. 7. The apparatus of claim 6 wherein said update by the control mechanism further causes the selected register to cycle through one of many possible programmable sets of registers, starting with a particular register within a set. 8. The apparatus of claim 1 further comprising a control mechanism operable such that each port's register index may be independently configured for an update method and a register address set, or optionally disabled for register file indexing. 9. The apparatus of claim 1 further comprising a crowd mechanism operable such that the RFI look ahead register associated with each register file port may be initialized automatically from a register field specified in an instruction. 10. A method of register file index (RFI) control comprising the steps of: establishing an RFI control specification in RFI control registers to specify RFI control and address information for at least one register ports port used by a particular execution unit or units; establishing RFI initialization control: ; performing RFI update control for updating a register port address in one of the RFI control registers associated with the at least one register port; executing an RFI instruction as part of a first indirect approach to select an instruction for execution; and specifying the register port addresses address utilizing the updated register port address as part of a double second indirect approach to their select the specification of the register port address. 11. The method of claim 10 wherein said step of establishing RFI control specification is performed utilizing the RFI control registers specifying all the RFI control information for register ports accessed by a particular execution unit. 12. The method of claim 11 wherein the RFI control information specifies RFI register update policy. 13. The method of claim 10 wherein said step of establishing RFI initialization control comprises the steps of: writing control information into an RFI control register: ; and setting a bit in an RFI reset register (RFIRR) corresponding to a particular RFI control group and particular execution unit. 14. The method of claim 10 wherein the step of updating a look ahead register port address comprises the step of: updating an RFI look ahead register for the next cycle by adding or subtracting a constant from its the register port address stored in the look ahead register while maintaining its the register port address within a particular set of register addresses. 15. The method of claim 14 wherein said updating is performed by specifying an increment value and a register file divisor (RFD) for each port to be controlled. 16. The method of claim 10 wherein the step of RFI instruction execution is enabled through control information contained in instruction words. 17. The method of claim 16 wherein said control information specifies whether standard register selection operand fields are used or whether RFI selection of registers is to be used. 18. The method of claim 16 wherein the control information indirectly specifies another control register or set of registers which are used to directly control RFI operation. 19. A method for data processing with register file indexing (RFI), the method including: receiving a plurality of instruction words for execution; reading, based on a start of an RFI sequence indication stored in an RFI control register, a field in each of the plurality of instruction words to directly specify a first plurality of operand addresses of a plurality of registers, the plurality of registers as addressed by the first plurality of operand addresses containing a first plurality of data operands; writing a second plurality of operand addresses to a look ahead register based on the first plurality of operand addresses as controlled by control circuitry and RFI control registers; executing the plurality of instruction words in parallel utilizing the first plurality of data operands; clearing the start of the RFI sequence indication; specifying the second plurality of operand addresses of the plurality of registers by reading, based on the cleared start of the RFI sequence indication, the contents of the look ahead register, the plurality of registers as addressed by the second plurality of operand addresses containing a second plurality of data operands; and executing the plurality of instruction words in parallel utilizing the second plurality of data operands. 20. The method of claim 19 wherein the control circuitry of the writing step further comprises: adding or subtracting a constant to the first plurality of operand addresses. 21. The method of claim 19 further comprising: initializing an RFI control register from a register field specified in one of the plurality of instruction words. 22. A control circuit apparatus for operating in both a register file index (RFI) mode and non-RFI mode, the control circuit apparatus comprising: a register file storing a plurality of operands; an instruction register holding a first instruction and a first operand address of the register file for execution with the first instruction; RFI circuitry for calculating and holding a second operand address of the register file for execution with the first instruction; and a multiplexer having two inputs and an output, one of the two inputs connecting to the instruction register and the other of the two inputs connecting to the RFI circuitry, the output connecting to the register file; and in response to a signal signaling RFI mode, the multiplexer selecting the first operand address during a first execution cycle and the second operand address during a second execution cycle; and upon loading the instruction register with a second instruction having a third operand address and in response to the RFI signal signaling non-RFI mode, the multiplexer selecting the third operand address; and the selected operand address specifying the operand from the register file for use by an execution unit when executing the first instruction or the second instruction in a third execution cycle. 23. The control circuit apparatus of claim 22 wherein the multiplexer selects the second operand address for execution cycles subsequent to the third execution cycle. 24. The control circuit apparatus of claim 22 wherein the RFI signal dependent on a bit in the instruction register. 25. The control circuit apparatus of claim 22 disposed in a VLIW processor. 26. The control circuit apparatus of claim 22 disposed in a iVLIW processor. 27. The control circuit apparatus of claim 22 wherein the second operand address represents the end of a block of operand addresses. 28. The control circuit apparatus of claim 22 wherein the RFI circuitry comprises an adder circuit for calculating the second operand address and a look ahead register storing the second operand address. 29. The control circuit apparatus of claim 28 wherein the RFI circuitry further comprises update control logic controlling the adder circuit for calculating the second operand address. 30. The control circuit apparatus of claim 28 wherein the second instruction is not loaded until a block of operand addresses have been calculated and executed. 31. The control circuit apparatus of claim 22 wherein the RFI mode or non-RFI mode are indications based upon information contained in the instruction register which are valid for the execution of each instruction loaded into the instruction register. 32. The control circuit apparatus of claim 22 wherein the second operand address is initialized prior to RFI operation by pre-setup loading of an initial second operand address. 33. The control circuit apparatus of claim 22 wherein the second operand address is calculated according to an increment value stored in the RFI circuitry. 34. The control circuit apparatus of claim 33 wherein the RFI circuitry comprises: a modulo adder circuit for calculating the second operand address based on a current operand address, the increment value, and a block size; and a look ahead register storing the second operand address and supplying the second operand address to the multiplexer. 35. The control circuit apparatus of claim 22 wherein the second operand address Rnext is calculated upon each receipt of the signal signaling RFI mode according to Rnext=((Rcurrent+k)mod M)+Q*M, wherein Rcurrent is the current value of the second operand address prior to calculating, k is an increment value, M is a block size, and Q is a floor quotient └Rs/M┘ for a starting register operand address Rs and wherein Rcurrent is equal to Rs for the first calculation of an RFI sequence. 36. A method of operating in both a register file index (RFI) mode and non-RFI mode, the method comprising: receiving a first instruction having a first operand address; receiving a signal indicating RFI mode; calculating a second operand address based on the first operand address; selecting the first operand address; retrieving an operand using the first operand address; executing the first instruction with the retrieved operand; selecting the second operand address; retrieving an operand using the second operand address; executing the first instruction with the retrieved operand; receiving a second instruction; receiving a signal indicating non-RFI mode; selecting a third operand address carried in the second instruction; retrieving an operand using the third operand address; and executing the second instruction with the retrieved operand. 37. The method of claim 36 wherein the second operand address represents the end of a block of operand addresses to be executed with the first instruction. 38. The method of claim 36 wherein the received signal indicating RFI mode is based on a bit in the first instruction. 39. The method of claim 36 wherein the received signal indicating RFI mode is based on a miscellaneous register file. 40. The method of claim 36 wherein the received signal indicating RFI mode is based on the opcode carried in the receiving instruction. 41. The method of claim 36 further comprising, before the step of selecting the second operand address, the step comprising: receiving a third instruction; receiving a signal indicating non-RFI mode; selecting a fourth operand address carried in the third instruction; retrieving an operand address using the fourth operand address; and executing a third instruction, the third instruction operating in a non-RFI mode. 42. The method of claim 36 wherein the calculating step comprises adding or subtracting from the first operand address. 43. The method of claim 36 wherein the calculating step comprises updating the second operand address upon each receipt of the signal indicating RFI mode. 44. The method of claim 43 further comprising: initializing the second operand address prior to RFI operation with a pre-setup initial second operand address. 45. The method of claim 43 further comprising: updating the second operand address according to an increment value. 46. The method of claim 45 further comprising: calculating in a modulo adder circuit the second operand address based on a current value of the second operand address, the increment value, and a block size. 47. The method of claim 43 further comprising: calculating the second operand address Rnext upon each receipt of the signal indicating RFI mode according to Rnext=((Rcurrent+k)mod M)+Q*M, wherein Rcurrent is the current value of the second operand address prior to calculating, k is an increment value, M is a block size, and Q is a floor quotient └Rs/M┘ for a starting register Rs and wherein Rcurrent is equal to Rs for the first calculation of an RFI sequence.