초록 ▼

A circuit interrupter includes band pass filters cooperating with a current sensor to output bands having different, non-overlapping ranges of frequencies, peak detectors cooperating with the filters to detect corresponding peak current values, envelope detectors cooperating with the filters to dete

A circuit interrupter includes band pass filters cooperating with a current sensor to output bands having different, non-overlapping ranges of frequencies, peak detectors cooperating with the filters to detect corresponding peak current values, envelope detectors cooperating with the filters to detect corresponding occurrences from the bands being within corresponding predetermined magnitude ranges, a counter counting the occurrences, and a processor providing and disabling series arc detection when sensed current is greater than a first predetermined value. The processor determines tallies responsive to peak current values exceeding corresponding thresholds, determines series arcing from sensed current being less than the first predetermined value for a predetermined time, the tally for a current half-cycle being nonzero, and a count for the current half-cycle being different than the count for an immediately previous half-cycle of like polarity by at least a second predetermined value. A series chaos accumulator is increased responsive to series arcing.

대표청구항 ▼

What is claimed is: 1. An arc fault circuit interrupter for an alternating current power circuit including a plurality of half-cycles, said arc fault circuit interrupter comprising: separable contacts; an operating mechanism structured to open and close said separable contacts; at least one current

What is claimed is: 1. An arc fault circuit interrupter for an alternating current power circuit including a plurality of half-cycles, said arc fault circuit interrupter comprising: separable contacts; an operating mechanism structured to open and close said separable contacts; at least one current sensor structured to sense current flowing through said separable contacts; a first band pass filter cooperating with one of said at least one current sensor to output a first pass band having a first range of frequencies of said sensed current; a second band pass filter cooperating with one of said at least one current sensor to output a second pass band having a second range of frequencies of said sensed current, said second range of frequencies not overlapping and being greater than said first range of frequencies; a first peak detector cooperating with said first band pass filter to detect a plurality of first peak current values from said first pass band; a second peak detector cooperating with said second band pass filter to detect a plurality of second peak current values from said second pass band; a first envelope detector cooperating with said first band pass filter to detect a plurality of first occurrences from said first pass band being within a first predetermined range of magnitudes; a second envelope detector cooperating with said second band pass filter to detect a plurality of second occurrences from said second pass band being within a second predetermined range of magnitudes; a counter structured to count said first and second occurrences; and a processor structured to provide series arc detection and cooperating with one of said at least one current sensor to disable said series arc detection when the sensed current is greater than a first predetermined value, said processor further cooperating with said counter to determine a plurality of counts from said counter for said half-cycles, said processor further cooperating with said first and second peak detectors to determine a plurality of tallies responsive to one of said first peak current values exceeding a first threshold for said half-cycles or one of said second peak current values exceeding a second threshold for said half-cycles, said processor being further structured to determine presence of series arcing in said power circuit from: said sensed current being less than said first predetermined value for at least a predetermined time, the tally for a current one of said half-cycles being not zero, and the count of said counter for the current one of said half-cycles being different than the count of said counter for an immediately previous one of said half-cycles of like polarity by at least a second predetermined value, said processor being further structured to increase a series chaos accumulator responsive to said presence of series arcing. 2. The arc fault circuit interrupter of claim 1 wherein said first and second thresholds are first and second lower thresholds, respectively, both of said first and second lower thresholds being structured to enable said processor to detect noise generated by a series arc fault; and wherein said processor is further structured to determine said plurality of tallies responsive to said one of said first peak current values exceeding said first lower threshold and being less than a third upper threshold for said half-cycles or said one of said second peak current values exceeding said second lower threshold for said half-cycles. 3. The arc fault circuit interrupter of claim 1 wherein said first and second thresholds are first and second lower thresholds, respectively; wherein said first band pass filter has an output that is input by said first peak detector; wherein said second band pass filter has an output that is input by said second peak detector; and wherein said processor is further structured to remove baseline shifting of the outputs of said peak detectors. 4. The arc fault circuit interrupter of claim 1 wherein the first range of frequencies of said first band pass filter is about 100 kHz+/-3.125 kHz; and wherein the second range of frequencies of said second band pass filter is about 900 kHz+/-28.125 kHz. 5. The arc fault circuit interrupter of claim 1 wherein said first band pass filter is a two-stage band pass filter having a center frequency of about 100 kHz; and wherein said second band pass filter is a two-stage band pass filter having a center frequency of about 900 kHz. 6. The arc fault circuit interrupter of claim 1 wherein the minimum frequency of said first range of frequencies is about 50 kHz; wherein the maximum frequency of the second range of frequencies is about 2 MHz; and wherein each of said first and second band pass filters have a center frequency to bandwidth ratio of greater than about 5. 7. The arc fault circuit interrupter of claim 1 wherein said first predetermined value is about 30 ARMS. 8. The arc fault circuit interrupter of claim 1 wherein said counter structured to count said first and second occurrences is structured to count high frequency pulses for each of said half-cycles to eliminate load noise associated with periodic high frequency signals. 9. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to determine if said series chaos accumulator is negative and to responsively set said series chaos accumulator to zero. 10. The arc fault circuit interrupter of claim 1 wherein said processor comprises an output; and wherein said processor is further structured to determine the occurrence of a series arc fault when said series chaos accumulator is greater than a third predetermined value and to responsively set the output of said processor to cause said operating mechanism trip open said separable contacts. 11. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to increase said series chaos accumulator by a predetermined amount responsive to said presence of series arcing. 12. The arc fault circuit interrupter of claim 1 wherein said processor is further structured to decrease said series chaos accumulator by a predetermined amount when said processor does not determine said presence of series arcing in said power circuit. 13. A method of detecting series arc faults for an alternating current power circuit including a plurality of half-cycles, said method comprising: sensing current flowing through said power circuit and outputting a sensed current value; employing a first band pass filter to output a first pass band having a first range of frequencies of said sensed current value; employing a second band pass filter to output a second pass band having a second range of frequencies of said sensed current value, said second range of frequencies not overlapping and being greater than said first range of frequencies; detecting a plurality of first peak current values from said first pass band; detecting a plurality of second peak current values from said second pass band; detecting a plurality of first occurrences from said first pass band being within a first predetermined range of magnitudes; detecting a plurality of second occurrences from said second pass band being within a second predetermined range of magnitudes; counting said first and second occurrences and outputting a count value; providing series arc detection and disabling said series arc detection when said sensed current value is greater than a first predetermined value; determining a plurality of counts from said count value for said half-cycles; determining a plurality of tallies responsive to one of said first peak current values exceeding a first threshold for said half-cycles or one of said second peak current values exceeding a second threshold for said half-cycles; determining presence of series arcing in said power circuit from: (1) said sensed current value being less than said first predetermined value for at least a predetermined time, (2) the tally for a current one of said half-cycles being not zero, and (3) the count for the current one of said half-cycles being different than the count for an immediately previous one of said half-cycles of like polarity by at least a second predetermined value; and increasing a series chaos accumulator responsive to said presence of series arcing. 14. The method of claim 13 further comprising employing the first range of frequencies of about 100 kHz+/-3.125 kHz; and employing the second range of frequencies of about 900 kHz+/-28.125 kHz. 15. The method of claim 13 further comprising employing a two-stage band pass filter having a center frequency of about 100 kHz as said first band pass filter; and employing a two-stage band pass filter having a center frequency of about 900 kHz as said second band pass filter. 16. The method of claim 13 further comprising employing the minimum frequency of said first range of frequencies of about 50 kHz; employing the maximum frequency of said second range of frequencies of about 2 MHz; and employing a center frequency to bandwidth ratio for each of said first and second band pass filters of greater than about 5. 17. The method of claim 13 further comprising determining the occurrence of a series arc fault when said series chaos accumulator is greater than a third predetermined value and responsively interrupting said current flowing through said power circuit. 18. The method of claim 13 further comprising periodically sampling the first peak current values from said first pass band; periodically sampling the second peak current values from said second pass band; and introducing random variations in said periodically sampling of said first peak current values from said first pass band and said second peak current values from said second pass band. 19. The method of claim 13 further comprising employing first and second lower thresholds as said first and second thresholds, respectively; removing baseline shifting of said plurality of first peak current values detected from said first pass band; and removing baseline shifting of said plurality of second peak current values detected from said second pass band. 20. The method of claim 19 further comprising employing a first moving average during said removing baseline shifting of said plurality of first peak current values detected from said first pass band; employing a second moving average during said removing baseline shifting of said plurality of second peak current values detected from said second pass band; and disabling said series arc detection for a predetermined time if said first moving average or said second moving average is greater than a predetermined value. 21. The method of claim 13 further comprising determining a tripping time based upon said sensed current value; determining if said series chaos accumulator is greater than a third predetermined value before said determined tripping time, and responsively waiting without tripping a circuit breaker until a predetermined time before said determined tripping time; and during said responsively waiting, determining if there is said presence of series arcing and responsively tripping said circuit breaker, and, otherwise, resetting said series chaos accumulator to zero.