초록 ▼

A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Request

A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.

대표청구항 ▼

What is claimed is: 1. A bank-access scheduler comprising: a plurality of requester inputs for carrying requests for memory access to a shared memory from a plurality of requestors; a plurality of bank interfaces to the shared memory, each bank interface for accessing a bank of the shared memory, w

What is claimed is: 1. A bank-access scheduler comprising: a plurality of requester inputs for carrying requests for memory access to a shared memory from a plurality of requestors; a plurality of bank interfaces to the shared memory, each bank interface for accessing a bank of the shared memory, wherein banks are interleaved with a bank granularity; a plurality of request selectors coupled to the plurality of bank interfaces, each request selector for selecting a selected requester from the plurality of requester inputs to the request selector; and staggering means for staggering connection of the plurality of request inputs to the plurality of bank interfaces wherein each request input is connected to a different bank interface in the plurality of bank interfaces for each time-slot in a sequence of time-slots; wherein the plurality of requesters comprises: a packet interface for requesting writing of incoming packets from an external network to the shared memory; a plurality of multi-processor tribes, each multi-processor tribe comprising a plurality of processors, each processor for operating on a packet written to the shared memory by the packet interface; wherein an incoming packet from the packet interface is written to a next-available bank in the shared memory; wherein a first bank in the shared memory is a page-start bank for storing a start of an aligned page; wherein an offset bank in the shared memory does not contain the start of the aligned page; wherein the aligned page starts at an address having all zero address bits for address bits having a significance less than a size of the aligned page; wherein the next-available bank is an offset bank when the incoming packet arrives when the first bank is not immediately available to be written by the packet interface; whereby requests are connected to banks of the shared memory in a staggered fashion and whereby incoming packets are able to be written to the offset bank as the next-available bank. 2. The bank-access scheduler of claim 1 wherein the staggering means comprises staggering connections of requestor inputs to physical inputs to the plurality of request selectors, wherein each requestor input is applied to different logical inputs in a sequence of logical inputs of each request selector, whereby physical connection of inputs to the plurality of request selectors is staggered. 3. The bank-access scheduler of claim 1 wherein the sequence of time-slots comprises 8 time-slots; wherein the plurality of request selectors comprises 8 request selectors and the shared memory comprises 8 banks. 4. A bank-access scheduler comprising: a plurality of requestor inputs for carrying requests for memory access to a shared memory from a plurality of requesters; a plurality of bank interfaces to the shared memory, each bank interface for accessing a bank of the shared memory, wherein banks are interleaved with a bank granularity; a plurality of request selectors coupled to the plurality of bank interfaces, each request selector for selecting a selected requestor from the plurality of requestor inputs to the request selector; and staggering means for staggering connection of the plurality of request inputs to the plurality of bank interfaces wherein each request input is connected to a different bank interface in the plurality of bank interfaces for each time-slot in a sequence of time-slots; a time-slot counter for generating a count value that varies for each time-slot in the sequence of time-slots; wherein the count value is applied as a select input to the plurality of request selectors; a packet-offset generator, coupled to the time-slot counter, for generating a packet offset that indicates a starting location within a page in the shared memory for storage of an incoming packet; wherein the packet offset is a function of the count value from the time-slot counter whereby the count value controls selection by the plurality of request selectors and whereby requests are connected to banks of the shared memory in a staggered fashion. 5. The bank-access scheduler of claim 4 wherein the packet offset is generated as the count value from the time-slot counter multiplied by the bank granularity. 6. The bank-access scheduler of claim 5 wherein incoming packets have a size that is variable from packet to packet. 7. A bank-access scheduler comprising: a plurality of requester inputs for carrying requests for memory access to a shared memory from a plurality of requesters; a plurality of bank interfaces to the shared memory, each bank interface for accessing a bank of the shared memory, wherein banks are interleaved with a bank granularity; a plurality of request selectors coupled to the plurality of bank interfaces, each request selector for selecting a selected requester from the plurality of requester inputs to the request selector; and staggering means for staggering connection of the plurality of request inputs to the plurality of bank interfaces wherein each request input is connected to a different bank interface in the plurality of bank interfaces for each time-slot in a sequence of time-slots; wherein each multi-processor tribe further comprises: a slot scheduler receiving random-access requests from a plurality of processors, for generating a stream of requests for access to the banks of the shared memory in a sequence of banks that are accessible by the slot scheduler during the sequence of time-slots; wherein the slot scheduler further comprises: a priority counter that advances through a priority sequence when a processor in the plurality of processors has a requests selected for access to the banks; a direction bit that is toggled when the priority counter wraps around to a reset value, the direction bit indicating a direction of priority in the priority sequence; and a request selector that chooses a highest-priority request from the plurality of processors using the priority sequence and the direction bit, wherein request starvation is prevented and a minimum worst-case latency is provided; whereby requests are connected to banks of the shared memory in a staggered fashion and whereby random-access requests are converted to the stream of requests to banks of the shared memory in the sequence of banks. 8. A packet-processing system comprising: a shared memory divided into a plurality of banks, the plurality of banks being word-interleaved, wherein successive words in a stream of words having a sequence of word-incremented addresses are stored to successive banks in the plurality of banks; a plurality of requesters that request access to the shared memory, the plurality of requesters comprising: a packet interface coupled to an external network, the packet interface receiving incoming packets from the external network and outputting egress packets to the external network; a first multi-processor tribe; wherein the first multi-processor tribe comprises: a plurality of processors, each processor for operating on a packet initially stored in the shared memory by the packet interface; and a slot scheduler that receives requests from the plurality of processors and generates a pseudo-sequential stream of requests to successive banks in the plurality of banks; wherein the plurality of requesters form a looping list of requestors; a parallel staggered round-robin arbiter for connecting the plurality of requesters to the plurality of banks to allow parallel accesses to the shared memory during a time-slot, the parallel staggered round-robin arbiter comprising a plurality of selectors, each selector for controlling access to a bank in the plurality of banks; wherein each selector selects successive requesters in the looping list of requesters during successive time-slots; wherein each selector selects a different requester in the looping list of requesters for a first time-slot; an offset generator, activated by the packet interface writing a start of an incoming packet to a selected bank in the plurality of banks, the offset generator generating an offset for the incoming packet that specifies the selected bank in the plurality of banks; wherein the selected bank is able to be selected from any bank in the plurality of banks; wherein the offset is sent to an assigned processor in the plurality of processors for the first multi-processor tribe when the assigned processor is instructed to begin operating on the incoming packet stored in the shared memory; whereby the offset is generated and sent to the assigned processor to indicate the selected bank storing the start of the incoming packet and whereby selectors stagger selection of successive requesters in the looping list of requesters to successive banks for parallel access to the shared memory. 9. The packet-processing system of claim 8 further comprising: a second multi-processor tribe; wherein the second multi-processor tribe comprises: a second plurality of processors, each processor for operating on a packet initially stored in the shared memory by the packet interface; and a second slot scheduler that receives requests from the second plurality of processors and generates a pseudo-sequential stream of requests to successive banks in the plurality of banks; wherein the plurality of banks comprises 8 banks and the looping list of requesters comprises 8 requesters, wherein 8 banks are accessible in parallel for each time-slot. 10. The packet-processing system of claim 9 wherein the plurality of requesters further comprises: a control interface for sending data from the shared memory to an external host processor. 11. A packet-processing system comprising: a shared memory divided into a plurality of banks, the plurality of banks being word-interleaved, wherein successive words in a stream of words having a sequence of word-incremented addresses are stored to successive banks in the plurality of banks; a plurality of requesters that request access to the shared memory, the plurality of requesters comprising: a packet interface coupled to an external network, the packet interface receiving incoming packets from the external network and outputting egress packets to the external network; a first multi-processor tribe; wherein the first multi-processor tribe comprises: a plurality of processors, each processor for operating on a packet initially stored in the shared memory by the packet interface; and a slot scheduler that receives requests from the plurality of processors and generates a pseudo-sequential stream of requests to successive banks in the plurality of banks; wherein the plurality of requesters form a looping list of requestors; a parallel staggered round-robin arbiter for connecting the plurality of requesters to the plurality of banks to allow parallel accesses to the shared memory during a time-slot, the parallel staggered round-robin arbiter comprising a plurality of selectors, each selector for controlling access to a bank in the plurality of banks; wherein each selector selects successive requesters in the looping list of requesters during successive time-slots; wherein each selector selects a different requester in the looping list of requesters for a first time-slot; wherein the slot scheduler comprises: a bank counter, synchronized to the parallel staggered round-robin arbiter, for generating a bank count indicating a current bank in the plurality of banks that the multi-processor tribe can access during a current time-slot; a bank matcher, receiving a plurality of requests from the plurality of processors in the multi-processor tribe, for selecting matching requests matching the bank count from the bank counter; and a prioritizer that selects a current request from the matching requests from the bank matcher, the current request being sent to the parallel staggered round-robin arbiter during the current time-slot for access to the current bank, whereby multiple requests from processors are matched to the bank count and prioritized to select the current request and whereby selectors stagger selection of successive requesters in the looping list of requesters to successive banks for parallel access to the shared memory. 12. The packet-processing system of claim 11 wherein each selector comprises an N-to-1 multiplexer for selecting from among N requesters in the looping list of requestors. 13. The packet-processing system of claim 11 wherein a frequently-accessed field of the incoming packet is able to be stored in any bank in the plurality of banks, whereby frequently-accessed fields of a plurality of incoming packets are stored across all banks of the shared memory. 14. A method for streaming an incoming packet into a shared memory for operating on the incoming packet in a packet processor comprising: receiving the incoming packet from an external network at a packet interface; determining a next bank in a plurality of interleaved banks, the next bank being accessible by the packet interface during a next time-slot while other banks in the plurality of interleaved banks are not accessible by the packet interface during the next time-slot; writing a start of the incoming packet to the next bank during the next time-slot; subsequently writing a remainder of the incoming packet to a sequence of banks in the plurality of banks over a sequence of time-slots that follow the next time-slot; generating a packet offset for the incoming packet from an indicator of the next bank, the packet offset indicating an offset from a start of a page aligned to a first bank in the plurality of banks; and sending the offset and a page identifier that identifies a memory page containing the incoming packet to an assigned processor in a plurality of processors, whereby incoming packets are streamed into the shared memory at offsets to memory pages. 15. The method of claim 14 further comprising: operating on the incoming packet by executing instructions on the assigned processor, and reading the incoming packet in the shared memory by requesting access to the shared memory using the offset and page sent to the assigned processor to locate the incoming packet in the shared memory, wherein the start of the incoming packet is stored to the next bank before the offset is sent to the assigned processor.