최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
---|---|
국제특허분류(IPC7판) |
|
출원번호 | UP-0440624 (2006-05-24) |
등록번호 | US-7638850 (2010-01-07) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 3 인용 특허 : 497 |
A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in
A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
What is claimed is: 1. A non-volatile memory array comprising: columns of channels in a semiconductor substrate; columns of junctions at the edges of said channels; columns of diffusion bit lines between said junctions; polysilicon gates over charge trapping dielectric over said portions of said ch
What is claimed is: 1. A non-volatile memory array comprising: columns of channels in a semiconductor substrate; columns of junctions at the edges of said channels; columns of diffusion bit lines between said junctions; polysilicon gates over charge trapping dielectric over said portions of said channels and overlapping at least portions of said junctions; a polysilicon spacer which forms at least a portion of said polysilicon gates; and bit line oxides extending to a height of said polysilicon gates under polysilicon word lines and are shorter than a height between said polysilicon word lines. 2. The array according to claim 1 and wherein said junctions are pocket implants. 3. The array according to claim 1 and wherein said polysilicon gates are at least partially formed of a first polysilicon layer and at least a portion of a polysilicon spacer. 4. The array according to claim 1 and wherein said polysilicon gates are at least partially formed of a first polysilicon layer. 5. The array according to claim 1 and further comprising bit line oxides extending to a height above said polysilicon gates. 6. The array according to claim 1 and further comprising bit line oxides extending to a height of said polysilicon gates. 7. The array according to claim 1 and further comprising bit line oxides next to said polysilicon gates and said oxides being wider at a top thereof than at a bottom thereof.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.