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A system and method increase yield from semiconductor wafer electroplating. The aspects include a semiconductor wafer, the semiconductor wafer comprising a plurality of die areas. A plating ring for holding the semiconductor wafer in position during electroplating is also included, the plating ring

A system and method increase yield from semiconductor wafer electroplating. The aspects include a semiconductor wafer, the semiconductor wafer comprising a plurality of die areas. A plating ring for holding the semiconductor wafer in position during electroplating is also included, the plating ring substantially surrounding a circumference of the semiconductor wafer and having a width that varies in order to avoid overlap near edge die areas of the semiconductor wafer.

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We claim: 1. A system for increasing yield from semiconductor wafer electroplating, the system comprising: a plating ring for holding a semiconductor wafer in position during electroplating, the semiconductor wafer comprising a plurality of die areas, the plating ring substantially surrounding a ci

We claim: 1. A system for increasing yield from semiconductor wafer electroplating, the system comprising: a plating ring for holding a semiconductor wafer in position during electroplating, the semiconductor wafer comprising a plurality of die areas, the plating ring substantially surrounding a circumference of the semiconductor wafer and overlapping an outside edge of the semiconductor wafer when the semiconductor wafer is positioned within the plating ring, the plating ring having a width that varies, the width narrowing near edge die areas of the semiconductor wafer to reduce overlap by the plating ring near edge die areas of the semiconductor wafer when the semiconductor wafer is positioned within the plating ring. 2. The system of claim 1 wherein the plating ring further comprises a plurality of portions having less than a maximum ring width. 3. The system of claim 2 wherein the plurality of portions further comprises four portions. 4. The system of claim 3 wherein the four portions avoid overlap with edge die areas on a top-most, bottom-most, left-most, and right-most section of the semiconductor wafer. 5. The system of claim 2 wherein the plurality of portions further comprises eight portions. 6. The system of claim 5 wherein the eight portions avoid overlap with edge die areas on a top-most, bottom-most, left-most, and right-most section of the semiconductor wafer, as well as edge die areas on sections approximately half-way between the top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer. 7. The system of claim 1 wherein the plating ring has a width that varies between approximately 5 millimeters and approximately 3 millimeters. 8. A method for increasing yield from semiconductor wafer electroplating, the method comprising: providing a plating ring with a plurality of portions having less than a maximum ring width; and utilizing the plating ring for holding a semiconductor wafer in position during electroplating, the plating ring substantially surrounding a circumference of the semiconductor wafer and overlapping an outside edge of the semiconductor wafer when the semiconductor wafer is positioned within the plating ring during electroplating, the plurality of portions positioned near edge die areas of the semiconductor wafer to reduce overlap by the plating ring near edge die areas of the semiconductor wafer when the semiconductor wafer is positioned within the plating ring during electroplating. 9. The method of claim 8 wherein the plurality of portions further comprises four portions. 10. The method of claim 9 wherein the four portions avoid overlap with edge die areas on a top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer. 11. The method of claim 8 wherein the plurality of portions further comprises eight portions. 12. The method of claim 11 wherein the eight portions avoid overlap with edge die areas on a top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer, as well as edge die areas on sections approximately half-way between the top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer. 13. The method of claim 8 wherein the maximum width further comprises a width of approximately 5 millimeters. 14. The method of claim 13 wherein each of the plurality of portions comprises a width of approximately 3 millimeters. 15. An apparatus for use in holding a semiconductor wafer in position during electroplating, the apparatus comprising: a plating ring having a plurality of reduced width portions, the plating ring substantially surrounding a circumference of a semiconductor wafer and overlapping an outside edge of the semiconductor wafer when the semiconductor wafer is positioned within the plating ring, the plurality of reduced width portions positioned to reduce overlap by the plating ring near edge die areas of the semiconductor wafer when the semiconductor wafer is positioned within the plating ring to increase die yield. 16. The apparatus of claim 15 wherein the plurality of reduced width portions further comprises four portions. 17. The apparatus of claim 16 wherein the four portions avoid overlap with edge die areas on a top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer. 18. The apparatus of claim 15 wherein the plurality of reduced width portions further comprises eight portions. 19. The apparatus of claim 18 wherein the eight portions avoid overlap with edge die areas on a top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer, as well as edge die areas on sections approximately half-way between the top-most, bottom-most, left-most, and right-most sections of the semiconductor wafer. 20. The apparatus of claim 15 wherein each of the plurality of reduced width portions comprises a width of approximately 3 millimeters.