IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
UP-0927377
(2004-08-27)
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등록번호 |
US-7647485
(2010-02-22)
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우선권정보 |
JP-2003-307061(2003-08-29) |
발명자
/ 주소 |
- Kami, Hirokazu
- Toi, Takao
- Awashima, Toru
- Anjo, Kenichiro
- Furuta, Koichiro
- Fujii, Taro
- Motomura, Masato
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출원인 / 주소 |
- NEC Corporation
- NEC Electronics Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
1 인용 특허 :
9 |
초록
▼
A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution m
A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.
대표청구항
▼
What is claimed is: 1. A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device
What is claimed is: 1. A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix, and said parallel arithmetic device having a function to temporarily halt said state transitions; said data processing system comprising: an operation execution means for causing said parallel arithmetic device to execute said state transitions in accordance with said object code; a device halt means for temporarily halting said state transitions for each of said operating cycle of said parallel arithmetic device; a result output means for supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted; a resume input means for supplying as input a command to resume said state transitions; and an operation resumption means for causing said operation execution means to resume said state transitions upon the input of said resume command. 2. The data processing system according to claim 1, further comprising: source input means for receiving said source code as input; object generation means for detecting, from said source code that has been received, operation states of a plurality of stages that undergo successive transitions, and for generating a series of object code that is composed of said operation commands for each of successively switching operating cycles of said plurality of data processing circuits and said plurality of interconnection switching circuits; and a correspondence generation means for generating data that indicate correspondence between said source code and said object code; wherein said result output means refers to data of said correspondence that has been generated and supplies as output a portion of said source code that corresponds to said object code when said parallel arithmetic device is temporarily halted. 3. The system according to claim 1, wherein: said parallel arithmetic device separately includes: a matrix circuit unit in which said plurality of data processing circuits and said plurality of interconnection switching circuits are arranged in a matrix; and a state management unit for successively switching, for each operating cycle, operation commands of said matrix circuit unit; said plurality of data processing circuits individually execute said data processing in accordance with operation commands that are individually set; and said plurality of interconnection switching circuits individually switch-control the interconnection relations of said plurality of data processing circuits in accordance with operation commands that are individually set. 4. The system according to claim 1, further comprising: rewrite input means for receiving as input held data of at least one portion of said plurality of data processing circuits of said parallel arithmetic device that is temporarily halted together with a rewrite command; and data rewrite means for using said held data that are received together with said rewrite command to rewrite corresponding held data of said parallel arithmetic device that is temporarily halted. 5. The system according to claim 1, wherein said parallel arithmetic device is implemented as a single unit. 6. A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; said data processing system comprising: an operation execution means for causing said parallel arithmetic device to execute said state transitions in accordance with said object code; a halt input means for receiving as input a halt command for said parallel arithmetic device together with a specific operation state; a device halt means for causing a temporary halt of said state transitions of said parallel arithmetic device during said operation state that was received together with said halt command; and a result output means for supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 7. The system according to claim 6, comprising: resume input means for receiving as input a command to resume said state transitions; and an operation resumption means for causing said operation execution means to resume said state transitions upon input of said resume command. 8. The system according to claim 6, further comprising: source input means for receiving said source code as input; object generation means for detecting, from said source code that has been received, operation states of a plurality of stages that undergo successive transitions, and for generating a series of object code that is composed of said operation commands for each of successively switching operating cycles of said plurality of data processing circuits and said plurality of interconnection switching circuits; and a correspondence generation means for generating data that indicate correspondence between said source code and said object code; wherein: said halt input means receives as input line number of said source code as said operation state; and said device halt means refers to data of said correspondence and temporarily halts said state transitions of said parallel arithmetic device when said operation state corresponds to said line number that has been received as input. 9. A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; said data processing system comprising: an operation execution means for causing said parallel arithmetic device to execute said state transitions in accordance with said object code; a halt input means for receiving as input a halt command for said parallel arithmetic device together with a halt condition that uses at least a portion of held data of said plurality of data processing circuits; a device halt means for temporarily halting said state transitions of said parallel arithmetic device when said halt condition is satisfied; and a result output means for supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 10. The system according to claim 9, further comprising: source input means for receiving said source code as input; object generation means for detecting, from said source code that has been received, operation states of a plurality of stages that undergo successive transitions, and for generating a series of object code that is composed of said operation commands for each of successively switching operating cycles of said plurality of data processing circuits and said plurality of interconnection switching circuits; and a correspondence generation means for generating data that indicate correspondence between said source code and said object code; wherein: said halt input means receives as input a halt condition that uses a variable of said source code as said held data; and said device halt means refers to said correspondence and temporarily halts said state transitions of said parallel arithmetic device when said held data satisfies said halt condition. 11. A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; said data processing system comprising: a source input means for receiving said source code as input; object generation means for detecting operation states of a plurality of stages that make successive transitions based on said source code that has been received, and generating a series of object code that is composed of operation commands for each of successively switched operating cycles of said plurality of data processing circuits and said plurality of interconnection switching circuits; a correspondence generation means for generating data that indicate the correspondence between said source code and said object code; an operation execution means for causing said parallel arithmetic device to execute said state transitions in accordance with said object code that has been generated; a halt input means for receiving as input a halt command for said parallel arithmetic device together with a halt condition that uses a specific portion of said source code; a device halt means for referring to data of said correspondence that have been generated and temporarily halting said state transitions of said parallel arithmetic device during said object code that satisfies said halt condition; and a result output means for supplying as output at least one portion of held data, said interconnection relations, and said operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 12. The system according to claim 11, wherein said result output means refers to data that indicate said correspondence that has been generated and supplies as output a portion of said source code that corresponds to said object code when said parallel arithmetic device is temporarily halted. 13. The system according to claim 11, wherein: said source input means receives as input said source code of a plurality of lines in which variables are described; said correspondence generation means generates data that show correspondence between: as a specific portion of said source code, said variable and said line number; and a specific portion of said object code; said halt input means receives as input a halt condition that uses at least one of said variable and said line number as a specific portions of said source code; said device halt means refers to data of said correspondence, and temporarily halts said state transitions of said parallel arithmetic device during object code in which said halt condition is satisfied. 14. The system according to claim 11, wherein: said parallel arithmetic device separately includes: a matrix circuit unit in which said plurality of data processing circuits and said plurality of interconnection switching circuits are arranged in a matrix; and a state management unit for successively switching, for each operating cycle, operation commands of said matrix circuit unit; and said object generation means, when generating said object code from said source code, distinguishes between data paths that correspond to said matrix circuit unit and a finite state machine that corresponds to said state management unit. 15. A data processing system for debugging at least one of operation description source code and object code that cause, for each operating cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; said data processing system comprising: an operation execution means for causing said parallel arithmetic device to execute said state transitions in accordance with said object code; a halt input means for receiving as input a halt command for said parallel arithmetic device together with a halt condition; a halt generation means for generating object code that causes a portion of said plurality of data processing circuits and said interconnection switching circuits to function as the halt condition circuit that temporarily halts said state transitions in accordance with a halt condition that has been received as input; a halt insertion means for inserting object code of said halt condition circuit that has been generated into said operation description object code; and a result output means for supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 16. The system according to claim 15, wherein: said halt input means accepts an input of prescribed data; said halt generation means generates object code for causing a portion of said plurality of data processing circuits and said interconnection switching circuits to function as a function-adding circuit for adding a prescribed function to said parallel arithmetic device in accordance with said prescribed data; and said halt insertion means inserts object code of said function-adding circuit that has been generated into said operation description object code. 17. The system according to claim 15, wherein said halt insertion means inserts object code of said halt condition circuit into said operation description object code that is executed by said parallel arithmetic device that has been temporarily halted. 18. The system according to claim 17, wherein: said halt input means receives input of said halt command and said halt condition with said parallel arithmetic device in a temporarily halted state; and said halt generation means generates object code of said halt condition circuit with said parallel arithmetic device in a temporarily halted state. 19. The system according to claim 15, further comprising: source input means for receiving said source code as input; object generation means for detecting, from said source code that has been received, operation states of a plurality of stages that undergo successive transitions, and for generating a series of object code that is composed of said operation commands for each of successively switching operating cycles of said plurality of data processing circuits and said plurality of interconnection switching circuits; and a correspondence generation means for generating data that indicate correspondence between said source code and said object code; wherein: said halt input means receives as input said halt command for said parallel arithmetic device together with a halt condition that uses a specific portion of said source code; said halt generation means refers to said correspondence and generates object code of said halt condition circuit that corresponds to said halt condition; and said halt insertion means refers to data that indicate said correspondence and inserts object code of said halt condition circuit that has been generated into said operation description object code. 20. The system according to claim 15, wherein: said parallel arithmetic device causes at least one portion of said plurality of data processing circuits and said interconnection switching circuits to function as logical processing circuits by means of said operation description object code; said data processing system includes a vacant area detection means for detecting a vacant area that is composed of said data processing circuits and said interconnection switching circuits that are not used as said logical processing circuits; and said halt generation means generates object code that causes said data processing circuits and said interconnection switching circuits of said vacant area that has been detected to function as said halt condition circuit. 21. The system according to claim 15, wherein: said parallel arithmetic device causes at least one portion of said plurality of data processing circuits and said interconnection switching circuits to function as logical processing circuits by means of said operation description object code; said data processing system includes an arrangement adjusting means for causing said object generation means to re-generate object code of said logical processing circuits such that a vacant area is introduced for inserting said halt condition circuit of the object code that has been generated by said halt generation means; and said halt insertion means inserts object code of said halt condition circuit into said operation description object code such that said halt condition circuit is inserted in said vacant area. 22. The system according to claim 15 wherein: said parallel arithmetic device causes at least one portion of said plurality of data processing circuits and said interconnection switching circuits to function as logical processing circuits by means of said operation description object code; said object generation means generates object code of said logical processing circuits such that a vacant area is introduced in advance in which said halt condition circuit can be inserted; said halt insertion means inserts object code of said halt condition circuit into said operation description object code such that said halt condition circuit is inserted in said vacant area. 23. A data processing system for generating, from operation description source code that causes, for each operation cycle, successive transitions of operation states of a plurality of stages of a parallel arithmetic device, object code of said parallel arithmetic device; said parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix, said object code being composed of operation commands of said plurality of data processing circuits and said plurality of interconnection switching circuits that are successively switched for each of operating cycles; said data processing system comprising: a source input means for receiving said source code as input; object generation means for detecting, from said source code that has been received, operation states of a plurality of stages that undergo successive transitions for each of operating cycles that are successively switched and generating said object code; and correspondence generation means for generating data that indicate correspondence between said source code and said object code. 24. A data processing method for using a parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; the method comprising the steps of: causing said parallel arithmetic device to execute state transitions by means of operation description object code that causes, for each operating cycle, successive transitions of operation states of a plurality of stages of said parallel arithmetic device; temporarily halting said state transitions of said parallel arithmetic device for each of said operating cycles; reading and supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted; accepting input of a resume command of said state transitions; causing the resumption of said state transitions upon input of said resume command. 25. A data processing method for using a parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; the method comprising the steps of: receiving input of a haft command for said parallel arithmetic device and a specific operation state; causing said parallel arithmetic device to execute state transitions by means of operation description object code that causes, for each operating cycle, successive transitions of operation states of a plurality of stages of said parallel arithmetic device; temporarily halting said state transitions of said parallel arithmetic device at the time of said specific operation state that has been received as input together with said halt command; and reading and supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 26. The data processing method for using a parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; the method comprising the steps of: receiving input of a halt command for said parallel arithmetic device and a halt condition that uses at least a portion of held data of said plurality of data processing circuits; causing said parallel arithmetic device to execute state transitions by means of operation description object code that causes, for each operating cycle, successive transitions of operation states of a plurality of stages of said parallel arithmetic device; temporarily halting said state transitions of said parallel arithmetic device when said halt condition is satisfied; and reading and supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 27. The data processing method for using a parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; the method comprising the steps of: accepting source code as input; detecting, from said source code that has been accepted, operation states of a plurality of stages that undergo successive transitions, and generating a series of object code that describes operations that cause successive transitions of operation states of a plurality of stages of said parallel arithmetic device, and that is composed of, for each of operating cycles that are successively switched, operation commands of said plurality of data processing circuits and said plurality of interconnection switching circuits; generating data that indicate correspondence between said source code and said object code; receiving input of a halt command for said parallel arithmetic device and a halt condition that uses a specific portion of said source code; causing said parallel arithmetic device to execute said state transitions by means of said object code that has been generated; referring to said data of correspondence that have been generated and temporarily halting said state transitions of said parallel arithmetic device at a time of said object code in which said halt condition is satisfied; and reading and supplying as output at least one portion of held data, said interconnection relations, and said operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 28. A data processing method for using a parallel arithmetic device comprising a plurality of data processing circuits for individually executing modifiable data processing and a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits, said plurality of data processing circuits and said plurality of interconnection switching circuits being arranged in a matrix; the method comprising the steps of: receiving as input a halt command for said parallel arithmetic device and a halt condition; generating object code for causing a portion of said plurality of data processing circuits and said interconnection switching circuits to function as a halt condition circuit for temporarily halting said state transitions by means of said halt condition that has been received; inserting object code of said halt condition circuit that has been generated into operation description object code that causes, for each operating cycle, successive transitions of operation states of a plurality of stages of said parallel arithmetic device; causing said parallel arithmetic device to execute said state transitions by means of said operation description object code following insertion; and reading and supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of data processing circuits of said parallel arithmetic device that has been temporarily halted. 29. A parallel arithmetic device that causes, for each operating cycle, successive transitions of operation states of a plurality of stages in accordance with object code, said parallel arithmetic device comprising: a plurality of data processing circuits for individually executing modifiable data processing; a plurality of interconnection switching circuits for switch-controlling interconnection relations of said plurality of data processing circuits; temporary halt means for temporarily halting state transitions in accordance with at least external input; and transition resumption means for, in accordance with external input, causing resumption of said state transitions that have been temporarily halted; wherein said plurality of data processing circuits and said plurality of interconnection switching circuits are arranged in a matrix; and a result output means of supplying as output at least one portion of held data, said interconnection relations, and operation commands of said plurality of said data processing circuits of said parallel arithmetic device that has been temporarily halted. 30. The parallel arithmetic device according to claim 29, separately comprising: a matrix circuit unit in which said plurality of data processing circuits and said plurality of interconnection switching circuits are arranged in a matrix; and a state management unit for successively switching, for each operating cycle, operation commands of said matrix circuit unit, said state management unit including said temporary halt means and said transition resumption means.
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