초록 ▼

A device is provided for detecting temperature-induced delays in a combinational logic path. A signal at the output of the logic path is latched at a first latch using a primary clock signal. The primary clock signal is delayed by a delay element to provide a delayed clock signal. The output of the

A device is provided for detecting temperature-induced delays in a combinational logic path. A signal at the output of the logic path is latched at a first latch using a primary clock signal. The primary clock signal is delayed by a delay element to provide a delayed clock signal. The output of the logic path is latched at a second latch using the delayed clock signal. The delay element delays the clock signal by an amount that indicates the occurrence of an over-temperature condition at the logic path. A comparator compares the data latched at the first latch to the data latched at the second latch and provides an error signal indicative of an over-temperature condition if the first and second latch contain different data values.

대표청구항 ▼

What is claimed is: 1. A method comprising: receiving a first signal at a first combinational logic path of an integrated circuit, the first signal transitioning at a first time; providing a second signal from the first combinational logic path, the second signal transitioning at a second time in r

What is claimed is: 1. A method comprising: receiving a first signal at a first combinational logic path of an integrated circuit, the first signal transitioning at a first time; providing a second signal from the first combinational logic path, the second signal transitioning at a second time in response to the first signal transitioning at the first time; latching a first latch value based on the second signal in response to a clock signal changing state at a third time; delaying the clock signal to create a delayed clock signal; latching a second latch value based on the second signal in response to the delayed clock signal changing state at a fourth time, the delayed clock signal changing state in response to the clock signal changing state at the third time; and determining an over-temperature condition at the integrated circuit in response to the first latch value having a different logic value than the second latch value, and asserting an error signal in response to determining an over-temperature condition. 2. The method of claim 1, wherein the first combinational logic path is part of a native logic path, the first latch value is latched at the native logic path, delaying the clock signal to create the delayed clock signal occurs at a diagnostic logic path that determines whether the native logic path is operating properly, and the second latch value is latched at the diagnostic logic path. 3. The method of claim 1, wherein delaying the clock signal comprises delaying the clock signal based on a user programmable value. 4. The method of claim 1, wherein the first combinational logic path is a diagnostic logic path. 5. The method of claim 1, wherein the first combinational logic path is a diagnostic logic path, and delaying the clock signal comprises delaying the clock signal based upon a user programmable value. 6. The method of claim 1, further comprising latching the asserted error indicator signal. 7. The method of claim 6, wherein latching the asserted error indicator signal includes latching the asserted error indicator signal at a scan latch. 8. The method of claim 6, wherein latching the asserted error indicator signal includes latching the asserted error indicator signal at a register associated with a programmer's model of the integrated circuit. 9. The method of claim 1, wherein the method further comprises maintaining the error indicator signal in response to the first latch value and the second latch value as a sticky state at a sticky latch after asserting the error indicator signal. 10. The method of claim 9, wherein the method further comprises providing a signal to clear the error indicator signal. 11. The method of claim 9, wherein the method further comprises providing an external interrupt in response to asserting the error indicator signal. 12. A device comprising: a first latch comprising a data input and a clock input and an output; a first delay path comprising combinational logic, a first input coupled to the output of the first latch, and an output; a second latch comprising a data input coupled to the output of the first delay path, a clock input coupled to the clock input of first latch, and an output; a delay element comprising an input coupled to the clock input of the first latch and an output, the delay element to delay a signal at its output by an amount that indicates the occurrence of an over-temperature condition at the first delay path; a third latch comprising a data input coupled to the output of the first delay path, a clock input coupled to the output of the delay element, and an output; and a comparator comprising a first input coupled to the output of the second latch, a second input coupled to the output of the third latch, and an output. 13. The device of claim 12, wherein the first delay path and the second latch are part of a native logic path, and the delay element and the third latch are part of a diagnostic logic path. 14. The device of claim 12, wherein the delay element is a user programmable delay element. 15. The device of claim 12, wherein the comparator comprises a XOR gate comprising a first data input coupled to the output of the second latch, a second data input coupled to the output of the third latch, and an output. 16. The device of claim 15, wherein the comparator further comprises a sticky latch comprising a data input coupled to the output of the comparator, a reset input, and an output. 17. The device of claim 16, wherein the comparator further comprises an OR gate comprising a first input coupled to the output of the sticky latch, a second data input coupled to the output of the XOR gate, and an output coupled to the data input of the sticky latch. 18. The device of claim 16, wherein the comparator comprises a counter comprising a clock input and an output coupled to a latch. 19. The device of claim 18, farther comprising: a second delay element comprising a data input coupled to the clock input of the first latch and an output; a fourth latch comprising a data input coupled to the output of the first delay path, a clock input coupled to the output of the second delay element, and an output; and a second comparator comprising a first input coupled to the output of the second latch, a second input coupled to the output of the fourth latch, and an output. 20. A method comprising: receiving a first signal at a first combinational logic path of an integrated circuit, the first signal transitioning at a first time; providing a second signal from the first combinational logic path, the second signal transitioning at a second time in response to the first signal transitioning at the first time; latching a first latch value based on the second signal in response to a clock signal changing state at a third time; delaying the clock signal based upon a user programmable value to create a delayed clock signal; latching a second latch value based on the second signal in response to the delayed clock signal changing state at a fourth time, the delayed clock signal changing state in response to the clock signal changing state at the third time; and determining an over-temperature condition at the integrated circuit in response to the first latch value having a different logic value than the second latch value, and asserting an error signal in response to determining an over-temperature condition.