IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
UP-0803602
(2007-05-15)
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| 등록번호 |
US-7656236
(2010-03-31)
|
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발명자
/ 주소 |
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| 출원인 / 주소 |
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| 대리인 / 주소 |
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| 인용정보 |
피인용 횟수 :
7 인용 특허 :
272 |
초록
▼
A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a se
A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector is configured to operate at a first phase comparison frequency. The analog phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector is configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency.
대표청구항
▼
The invention claimed is: 1. A frequency synthesizer, comprising: an input terminal and an output terminal; a loop filter having a differential input; a digital phase detector comprising a first input coupled to the input terminal, a second input coupled to the output terminal, and an output couple
The invention claimed is: 1. A frequency synthesizer, comprising: an input terminal and an output terminal; a loop filter having a differential input; a digital phase detector comprising a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the differential input of the loop filter, wherein the digital phase detector is configured to operate at a first phase comparison frequency, and wherein the digital phase detector is configured to produce a first signal proportional to the phase difference between signals applied to the first and second inputs of the digital phase detector; and an analog phase detector comprising a first input coupled to the input terminal, a second input coupled to the output terminal, and a differential output alternating current (AC) coupled to the differential input of the loop filter, wherein the analog phase detector is configured to operate at a second phase comparison frequency, and wherein the analog phase detector is configured to produce a first differential signal corresponding to residual noise of the digital phase detector; wherein the first phase comparison frequency is different from the second phase comparison frequency. 2. The frequency synthesizer of claim 1, comprising a first frequency divider coupled between the output terminal and the first input of the digital phase detector. 3. The frequency synthesizer of claim 2, wherein the first frequency divider is a programmable integer divider. 4. The frequency synthesizer of claim 1, comprising a first frequency divider coupled between the first input of the digital phase detector and the output terminal and a second frequency divider coupled between the second input of the digital frequency detector and the input terminal, wherein the first and second frequency dividers are substantially identical and set the phase relationship at the first and second inputs of the digital phase detector to be in phase. 5. The frequency synthesizer of claim 4, wherein the analog phase detector is configured to produce a first differential signal corresponding to residual noise of the digital phase detector and the first and second frequency dividers. 6. The frequency synthesizer of claim 1, comprising a current to differential voltage converter coupled to the output of the digital phase detector to receive the first signal proportional to the phase difference between the signals applied to the first and second inputs of the digital phase detector and to output a second differential signal proportional to noise of the digital phase detector, wherein the second differential signal is direct current (DC) coupled to the differential input of the loop filter. 7. The frequency synthesizer of claim 6, comprising: wherein the first differential signal output of the analog phase detector is AC coupled to the second differential signal proportional to noise of the digital phase detector. 8. The frequency synthesizer of claim 1, comprising: an in-phase power splitter comprising an input coupled to the output terminal and a first output coupled to the first input of the digital phase detector and second output coupled to the first input of the analog phase detector. 9. The frequency synthesizer of claim 8, comprising: a quadrature phase power splitter comprising an input to receive a reference frequency signal coupled to the second input of the analog phase detector; and an in-phase output coupled to the second input of the digital phase detector. 10. The frequency synthesizer of claim 1, comprising a voltage controlled oscillator (VCO) coupled between the loop filter and the output terminal. 11. The frequency synthesizer of claim 10, comprising a frequency multiplier coupled between the VCO and the output terminal. 12. A method, comprising: receiving an output signal having a first frequency at a first input of an analog phase detector, receiving an input signal at the first frequency at a second input of the analog phase detector; receiving a first signal having a second frequency at a first input of a digital phase detector; receiving a second signal at the second frequency at a second input of the digital phase detector, wherein the first frequency is different from the second frequency; producing a first differential signal by the analog phase detector corresponding to a phase difference between the input signal and the output signal, wherein the first differential signal corresponds to noise of the digital phase detector; producing a second differential signal corresponding to a phase difference between the first and second signals, wherein the second differential signal is proportional to noise of the digital phase detector; and destructively combining the first and second differential signals at a differential input of a loop filter. 13. The method of claim 12, comprising: splitting the output signal into a third signal and a fourth signal, wherein the third and fourth signals are in in-phase relationship; and splitting the input signal into a fifth signal and a sixth signal, wherein the fifth and sixth signals are in quadrature-phase relationship. 14. The method of claim 13, comprising: receiving the third and the fifth signals at the respective first and second inputs of the analog phase detector, wherein the third and the fifth signals are in quadrature-phase relationship; producing the first differential signal by detecting the difference between the third signal and the fifth signal; receiving the fourth and the sixth signals at the respective first and second inputs of the digital phase detector, wherein the fourth and sixth signal are in in-phase relationship; and producing the second differential signal by detecting the phase difference between the fourth signal and the sixth signal. 15. The method of claim 14, comprising: direct current (DC) coupling the second differential signal to the differential input of the loop filter; and alternating current (AC) coupling the first differential signal to the differential input of the loop filter. 16. The method of claim 12, comprising: dividing the frequency of the output signal by a first integer by a first divider circuit to produce the first frequency; receiving the first frequency signal at the first input of the analog phase detector; dividing the first frequency by a second integer to produce the second frequency; and receiving the second frequency signal at the first input of the digital phase detector. 17. The method of claim 16, comprising: producing a first differential signal by the analog phase detector corresponding to a phase difference between the input signal and the output signal, wherein the first differential signal corresponds to noise of the digital phase detector and the first and second frequency dividers. 18. The method of claim 16, comprising: phase shifting the input signal; receiving the phase shifted input signal at the second input of the analog phase detector; dividing the frequency of the input signal by the first integer by a third divider circuit to produce the second frequency; and receiving the second frequency signal at the second input of the digital phase detector. 19. A compound phase locked loop, comprising: a programmable frequency divider to receive a sample of an output signal having a first frequency and to divide the output signal frequency by a first integer to produce an output signal at a second frequency; a quadrature power splitter to receive an input signal at the second frequency and to provide in-phase and quadrature output signals; a loop filter having a differential input; a digital phase detector comprising a first input coupled to an output of the programmable frequency divider, a second input coupled to the in-phase output of the quadrature power splitter, and an output coupled to the differential input of the loop filter, wherein the digital phase detector is configured to operate at a first phase comparison frequency, and wherein the digital phase detector is configured to produce a first signal proportional to the phase difference between signals applied to the first and second inputs of the digital phase detector; and an analog phase detector comprising a first input coupled to the output of the programmable frequency divider, a second input coupled to the quadrature output of the quadrature power splitter, and a differential output alternating current (AC) coupled to the differential input of the loop filter, wherein the analog phase detector is configured to operate at a second phase comparison frequency, and wherein the analog phase detector is configured to produce a first differential signal corresponding to residual noise of the digital phase detector; wherein the first phase comparison frequency is different from the second phase comparison frequency. 20. The compound phase locked loop of claim 19, comprising: an in-phase power splitter to split the output signal into a first and second signal, wherein the first and second signals are in in-phase relationship. 21. The compound phase locked loop of claim 19, comprising: a first frequency divider coupled between the first input of the digital phase detector and the output of the programmable frequency divider to divide the first frequency of the sample of the output signal by a second integer; and a second frequency divider coupled between the second input of the digital phase detector and the output of the in-phase output of the quadrature power splitter to divide the second frequency of the input signal by the second integer. 22. The compound phase locked loop of claim 19, comprising: a current to differential voltage converter coupled to the output of the digital phase detector to receive the first signal proportional to the phase difference between the signals applied to the first and second inputs of the digital phase detector and to output a second differential signal proportional to noise of the digital phase detector, wherein the second differential signal is direct current (DC) coupled to the differential input of the loop filter.
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