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Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

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What is claimed is: 1. A method comprising: associating a plurality of debugging registers with a core processor process and a debugging process; selectively setting at least one register control bit within a plurality of debugging registers to a prevent-transfer value for preventing transfer of da

What is claimed is: 1. A method comprising: associating a plurality of debugging registers with a core processor process and a debugging process; selectively setting at least one register control bit within a plurality of debugging registers to a prevent-transfer value for preventing transfer of data with respect to any of the plurality of debugging registers and the debugging process when a power transition sequence occurs within a digital signal processor; and setting at least one power control bit associated with the plurality of debugging registers to a prevent-power-transition value for preventing the power transition sequence of the digital signal processor when transferring data with respect to any of the plurality of debugging registers. 2. The method of claim 1, wherein the power transition sequence includes a power-down sequence. 3. The method of claim 1, wherein the debugging registers comprise a plurality of debugging configuration registers. 4. The method of claim 1, wherein the prevent-transfer value comprises an invalid status value and further comprising invalidating read/write transfers with respect to any of the debugging registers and the debugging process in the event of a power-up sequence of the core processor in response to the invalid status value. 5. The method of claim 1, wherein the prevent-transfer value comprises an invalid status value and further comprising invalidating read/write transfers with respect to any of the debugging registers and the debugging process in the event of a power-down sequence of the core processor in response to the invalid status value. 6. The method of claim 1, wherein the prevent-power-transition value comprises an interrupt-disabled value and further comprising disabling a power collapse during read/write transfers with respect to any of the debugging registers in response to the interrupt-disabled value. 7. The method of claim 1, further comprising setting the at least one register control bit to a permit-transfer value for permitting transferring data with respect to any of the plurality of debugging registers and the debugging process following a power-up sequence occurring within the digital signal processor. 8. The method of claim 1, further comprising setting the at least one power control bit to a permit-power-transition value for permitting a power transition sequence of the digital signal processor following an event of transferring data with respect to any of the plurality of debugging registers. 9. The method of claim 1, further comprising saving an existing debugging configuration in the plurality of debugging registers before the power transition sequence occurs. 10. The method of claim 1, wherein the at least one power control bit associated with the plurality of debugging registers is set to the prevent-power-transition value for preventing the power transition sequence of the digital signal processor when transferring data with respect to the plurality of debugging registers and the core processor process. 11. The method of claim 1, wherein the at least one power control bit associated with the plurality of debugging registers is set to the prevent-power-transition value for preventing the power transition sequence of the digital signal processor when transferring data with respect to the plurality of debugging registers and the debugging process. 12. A digital signal processor debugging system comprising: a plurality of debugging registers associated with a core processor process and a debugging process; at least one register control bit established within the plurality of debugging registers for controlling transfer of data with respect to any of the plurality of debugging registers and the debugging process, the at least one register control bit capable of being selectively set to a prevent-transfer value for preventing transfer of data with respect to any of the plurality of debugging registers and the debugging process in the event of a power transition sequence occurring within a digital signal processor; and at least one power control bit capable of being set to a prevent-power-transition value for preventing the power transition sequence of the digital signal processor in the event of transferring data with respect to any of the plurality of debugging registers. 13. The digital signal processor debugging system of claim 12, wherein the power transition sequence comprises a power-up sequence. 14. The digital signal processor debugging system of claim 12, wherein the power transition sequence comprises a power-down sequence. 15. The digital signal processor debugging system of claim 12, wherein the debugging registers comprise a plurality of debugging configuration registers. 16. The digital signal processor debugging system of claim 12, further comprising a trusted debugging process register for providing at least one trusted debugging control bit in confirming the debugging process to be a trusted debugging process. 17. The digital signal processor debugging system of claim 12, wherein the prevent-transfer value comprises an invalid status value and further comprising circuitry and instructions for invalidating read/write transfers with respect to any of the debugging registers and the debugging process in the event of a power-up sequence of the core processor in response to the invalid status value. 18. The digital signal processor debugging system of claim 12, wherein the prevent-transfer value comprises an invalid status value and further comprising circuitry and instructions for invalidating read/write transfers with respect to any of the debugging registers and the debugging process in the event of power-down sequence of the core processor in response to the invalid status value. 19. The digital signal processor debugging system of claim 12, wherein the prevent-power-transition value comprises an interrupt-disabled value and further comprising circuitry and instructions for disabling a power collapse during read/write transfers with respect to any of the debugging registers in response to the interrupt-disabled value. 20. The digital signal processor debugging system of claim 12, wherein the power transition sequence comprises a power-up sequence occurring within the digital signal processor. 21. The digital signal processor debugging system of claim 12, further comprising instructions and circuitry for setting the at least one power control bit to a permit-power-transition value for permitting a power transition sequence of the digital signal processor following the event of transfer of data with respect to any of the plurality of debugging registers. 22. A digital signal processor comprising: means for establishing within the plurality of debugging registers at least one register control bit for controlling transfer of data with respect to any of the plurality of debugging registers and a debugging process; means for selectively setting the at least one register control bit to a prevent-transfer value for preventing transfer of data with respect to any of the plurality of debugging registers and the debugging process in the event of a power transition sequence occurring within the digital signal processor; and means for setting at least one power control bit to a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transfer of data with respect to any of the plurality of debugging registers. 23. The digital signal processor system of claim 22, wherein the power transition sequence comprises a power-up sequence occurring within the digital signal processor. 24. The digital signal processor system of claim 22, wherein the power transition sequence comprises a power-down sequence within the digital signal processor. 25. The digital signal processor system of claim 22, wherein the debugging registers comprise a plurality of debugging configuration registers. 26. The digital signal processor system of claim 22, further comprising means for confirming the debugging process to be a trusted debugging process. 27. The digital signal processor system of claim 22, wherein the prevent-transfer value comprises an invalid status value and further comprising means for invalidating read/write transfers with respect to any of the debugging registers and the debugging process in the event of a power-up sequence in response to the invalid status value. 28. The digital signal processor system of claim 22, wherein the prevent-transfer value comprises an invalid status value and further comprising means for invalidating read/write transfers with respect to any of the debugging registers and the debugging process in the event of a power-down sequence of a core processor in response to the invalid status value. 29. The digital signal processor system of claim 22, wherein the prevent-power-transition value comprises an interrupt-disabled value and further comprising means for disabling a power collapse during read/write transfers with respect to any of the debugging registers in response to the interrupt-disabled value. 30. The digital signal processor system of claim 22, further comprising means for setting the at least one register control bit to a permit-power-transition value for permitting a power transition sequence of the digital signal processor following an event of transfer of data with respect to any of the plurality of debugging registers. 31. A computer usable medium having computer readable program code means embodied therein for processing instructions on a digital signal processor, the computer usable medium comprising: computer readable program code means for associating a plurality of debugging registers with a core processor process and a debugging process; computer readable program code means for establishing within the plurality of debugging registers at least one register control bit for controlling transfer of data with respect to any of the plurality of debugging registers and the debugging process; computer readable program code means for selectively setting the at least one register control bit to a prevent-transfer value for preventing transfer of data with respect to any of the plurality of debugging registers and the debugging process in the event of a power transition sequence occurring within the digital signal processor; and computer readable program code means for setting at least one power control bit to a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transfer of data with respect to any of the plurality of debugging registers. 32. The computer usable medium of claim 31, wherein the power transition sequence includes a power-down sequence occurring within the digital signal processor.