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An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four

An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

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The invention claimed is: 1. An apparatus for accessing a register file array in a data processing system comprising: a register file array having a plurality of entries, each entry having only two read ports and only two write ports; a plurality of input alignment multiplexers, coupled to the regi

The invention claimed is: 1. An apparatus for accessing a register file array in a data processing system comprising: a register file array having a plurality of entries, each entry having only two read ports and only two write ports; a plurality of input alignment multiplexers, coupled to the register file array, for receiving data from a data source and generating outputs for writing portions of the received data to entries in the register file array using one of the two write ports for entries in the register file array; and a plurality of output multiplexers coupled to the register file array, wherein outputs from the two read ports of the entries in the register file array are used to generate an input to one or more of the plurality of output multiplexers, and wherein the plurality of output multiplexers provide the data from entries of the register file array to an instruction decode unit of the data processing system. 2. The apparatus of claim 1, wherein that data is written to entries in the register file array in accordance with write word lines, wherein a first write word line is enabled for writes to a first port of each entry of each sub-array, and wherein a second write word line is enabled for writes to a second port of each entry of each sub-array. 3. The apparatus of claim 1, wherein the data source is an instruction cache, and wherein the register file array permits more than two writes of instruction data to the register file array and more than two reads of instruction data from the register file array in a single instruction cycle. 4. The apparatus of claim 1, wherein the plurality of entries in the register file array are partitioned into four sub-arrays, and wherein the output from a first read port of entries in a sub-array are combined together to generate a first sub-array output, and wherein the output from a second read port of entries in the sub-array are combined together to generate a second sub-array output. 5. The apparatus of claim 4, wherein the first sub-array output and second sub-array output are provided to one or more of the plurality of output multiplexers in accordance with a determined set of possible combinations of sub-array outputs for generating a predetermined number of read data outputs from the register file array. 6. The apparatus of claim 4, wherein a first sub-array of the register file array provides a zeroth sub-array output (Rd0) and a fourth sub-array output (Rd4), a second sub-array of the register file array provides a first sub-array output (Rd1) and a fifth sub-array output (Rd5), a third sub-array of the register file array provides a second sub-array output (Rd2) and a sixth sub-array output (Rd6), and a fourth sub-array of the register file array provides a third sub-array output (Rd3) and a seventh sub-array output (Rd7). 7. The apparatus of claim 6, wherein Rd0, Rd1, Rd2 and Rd3 are provided as inputs to a first output multiplexer, Rd1, Rd2, Rd3 and Rd4 are provided as inputs to a second output multiplexer, Rd2, Rd3, Rd4 and Rd5 are provided as inputs to a third output multiplexer, R3, Rd4, Rd5 and Rd6 are provided as inputs to a fourth output multiplexer, and Rd4, Rd5, Rd6 and Rd7 are provided as inputs to a fifth output multiplexer. 8. The apparatus of claim 7, wherein each of the first, second, third, fourth and fifth output multiplexers receive a select signal indicating which of the inputs provided to the multiplexers is to be output. 9. The apparatus of claim 8, wherein the select signals provided to the multiplexers are determined based on a start read address. 10. A method for accessing a register file array, having a plurality of entries in a data processing system comprising: receiving, by a plurality of input multiplexers, data from a data source and generating outputs for writing portions of the received data to entries in the register file array using one of only two write ports associated with each entry in the register file array; receiving a start read address for reading the data from the register file array; generating a first read word line and a second read word line for reading the data from the register file array, each entry having only two read ports, and wherein a first read port of each entry is associated with the first read word line and a second read port of each entry is associated with the second read word line; and reading the data from the register file array based on the start read address, the first read word line, and the second read word line to thereby generate data outputs from the register file array. 11. The method of claim 10, wherein the data outputs from the register file array are used to generate an input to one or more of a plurality of output multiplexers, and wherein the plurality of output multiplexers provide data from entries of the register file array to an instruction decode unit of the data processing system. 12. The method of claim 10, wherein the plurality of entries in the register file array are partitioned into four sub-arrays, and wherein the output from a first read port of entries in a sub-array are combined together to generate a first sub-array output, and wherein the output from a second read port of entries in the sub-array are combined together to generate a second sub-array output. 13. The method of claim 12, wherein the first sub-array output and second sub-array output are provided to one or more of the plurality of output multiplexers in accordance with a determined set of possible combinations of sub-array outputs for generating a predetermined number of read data outputs from the register file array. 14. The method of claim 12, wherein a first sub-array of the register file array provides a zeroth sub-array output (Rd0) and a fourth sub-array output (Rd4), a second sub-array of the register file array provides a first sub-array output (Rd1) and a fifth sub-array output (Rd5), a third sub-array of the register file array provides a second sub-array output (Rd2) and a sixth sub-array output (Rd6), and a fourth sub-array of the register file array provides a third sub-array output (Rd3) and a seventh sub-array output (Rd7). 15. The method of claim 14, wherein Rd0, Rd1, Rd2 and Rd3 are provided as inputs to a first output multiplexer, Rd1, Rd2, Rd3 and Rd4 are provided as inputs to a second output multiplexer, Rd2, Rd3, Rd4 and Rd5 are provided as inputs to a third output multiplexer, R3, Rd4, Rd5 and Rd6 are provided as inputs to a fourth output multiplexer, and Rd4, Rd5, Rd6 and Rd7 are provided as inputs to a fifth output multiplexer. 16. The method of claim 15, wherein each of the first, second, third, fourth and fifth output multiplexers receive a select signal indicating which of the inputs provided to the multiplexers is to be output. 17. The method of claim 10, wherein the data is written to entries in the register file array in accordance with write word lines, wherein a first write word line is enabled for writes to a first port of each entry of each sub-array, and wherein a second write word line is enabled for writes to a second port of each entry of each sub-array.