IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
UP-0463950
(2006-08-11)
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등록번호 |
US-7664920
(2010-04-04)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Sterne, Kessler, Goldstein & Fox, P.L.L.C.
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인용정보 |
피인용 횟수 :
2 인용 특허 :
21 |
초록
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A microprocessor includes a hierarchical memory subsystem, an instruction decoder, and a stream prefetch unit. The decoder decodes an instruction that specifies a locality characteristic parameter. In one embodiment, the parameter specifies a relative urgency with which a data stream specified by th
A microprocessor includes a hierarchical memory subsystem, an instruction decoder, and a stream prefetch unit. The decoder decodes an instruction that specifies a locality characteristic parameter. In one embodiment, the parameter specifies a relative urgency with which a data stream specified by the instruction is needed rather than specifying exactly which of the cache memories in the hierarchy to prefetch the data stream into. The prefetch unit selects one of the cache memory levels in the hierarchy for prefetching the data stream into based on the memory subsystem configuration and on the relative urgency. In another embodiment, the prefetch unit instructs the memory subsystem to mark the prefetched cache line for early, late, or normal eviction according to its cache line replacement policy based on the parameter value.
대표청구항
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I claim: 1. A method for prefetching a data stream into a microprocessor from a system memory coupled to the microprocessor, the microprocessor having a memory subsystem of a predetermined configuration, the configuration having a hierarchy of cache memories and each of the cache memories having a
I claim: 1. A method for prefetching a data stream into a microprocessor from a system memory coupled to the microprocessor, the microprocessor having a memory subsystem of a predetermined configuration, the configuration having a hierarchy of cache memories and each of the cache memories having a predetermined size, the method comprising: decoding an instruction, said instruction specifying the data stream and a parameter specifying a locality characteristic of said data stream, wherein the locality characteristic specifies a relative urgency with which said data stream is needed; and prefetching a cache line of the data stream from the system memory into the memory subsystem, wherein the microprocessor selects a cache memory level in the hierarchy for prefetching the cache line of the data stream into based on the memory subsystem configuration and on said relative urgency. 2. The method as recited in claim 1, wherein a first predetermined value of said parameter specifies said data stream is relatively urgently needed and wherein said prefetching comprises attempting to prefetch said cache line into a low level of the cache memory hierarchy relative to the memory subsystem configuration, wherein a second predetermined value of said parameter specifies said data stream is relatively non-urgently needed and wherein said prefetching comprises attempting to prefetch said cache line into a high level of the cache memory hierarchy relative to the memory subsystem configuration. 3. The method as recited in claim 2, wherein a third predetermined value of said parameter specifies said data stream is relatively moderately urgently needed and wherein said prefetching comprises attempting to prefetch said cache line into a middle level of the cache memory hierarchy relative to the memory subsystem configuration. 4. A method for prefetching a data stream into a microprocessor from a system memory coupled to the microprocessor, the microprocessor having a memory subsystem, the method comprising: decoding an instruction, said instruction specifying the data stream and a parameter specifying a locality characteristic of said data stream, wherein the locality characteristic specifies a relative ephemerality of the data stream; and prefetching a cache line of said data stream from the system memory into the memory subsystem, wherein the microprocessor marks the prefetched cache line of said data stream with a cache line replacement policy based on the memory subsystem configuration and on the relative ephemerality. 5. The method as recited in claim 4, further comprising marking, if said parameter specifies a second predetermined value, the prefetched cache line of said data stream as having a cache line replacement strategy of late eviction. 6. The method as recited in claim 5, wherein said cache line is marked as having a cache line replacement strategy of late eviction by setting said cache line as most-recently-used. 7. The method as recited in claim 4, further comprising marking, if said parameter specifies a third predetermined value, the prefetched cache line of said data stream as having a cache line replacement strategy of normal eviction. 8. The method as recited in claim 4, wherein said cache line is marked as having a cache line replacement strategy of early eviction by setting said cache line as least-recently-used. 9. A data stream prefetching microprocessor coupled to a system memory, comprising: a memory subsystem, having a predetermined configuration, said configuration having a hierarchy of cache memories and each of the cache memories having a predetermined size; an instruction decoder, configured to decode an instruction, said instruction specifying a data stream and a parameter specifying a locality characteristic of said data stream, wherein the locality characteristic specifies a relative urgency for which said data stream is needed; and a stream prefetch unit, coupled to said instruction decoder and said memory subsystem, comprising: a stream hit detector, coupled to said instruction decoder, configured to detect load instruction data addresses that hit in the data stream; and a stream prefetch engine, coupled to said stream hit detector, configured to prefetch a cache line of the data stream from the system memory into the memory subsystem in response to said stream hit detector detecting a load instruction data address that hits in the data stream, wherein said stream prefetch engine select[ing] a cache memory level in the hierarchy for prefetching the cache line of the data stream into based on the memory subsystem configuration and on . . . [said] relative urgency. 10. The microprocessor as recited in claim 9, wherein a first predetermined value of said parameter specifies said data stream is relatively urgently needed and wherein said stream prefetch engine is configured to attempt to prefetch said cache line into a low level of the cache memory hierarchy relative to the memory subsystem configuration, wherein a second predetermined value of said parameter specifies said data stream is relatively non-urgently needed, and wherein said stream prefetch engine is configured to attempt to prefetch said cache line into a high level of the cache memory hierarchy relative to the memory subsystem configuration. 11. The microprocessor as recited in claim 10, wherein a third predetermined value of said parameter specifies said data stream is relatively moderately urgently needed, and wherein said stream prefetch engine is configured to attempt to prefetch said cache line into a middle level of the cache memory hierarchy relative to the memory subsystem configuration. 12. A computer program product for use with a computing device, the computer program product comprising: a computer readable storage medium, having computer readable program code embodied thereon, for providing a data stream prefetching microprocessor coupled to a system memory, said computer readable program code comprising: first computer readable program code for providing a memory subsystem, having a predetermined configuration, said configuration having a hierarchy of cache memories and each of the cache memories having a predetermined size; second computer readable program code for providing an instruction decoder, configured to decode an instruction, said instruction specifying the data stream and a parameter specifying a locality characteristic of said data stream, wherein the locality characteristic specifies a relative urgency with which said data stream is needed rather than specifying exactly which of the cache memories in the hierarchy to prefetch said data stream into; and third computer readable program code for providing a stream prefetch unit, coupled to said instruction decoder and said memory subsystem, comprising: a stream hit detector, coupled to said instruction decoder, configured to detect load instruction data addresses that hit in the data stream; and a stream prefetch engine, coupled to said stream hit detector, configured to prefetch a cache line of the data stream from the system memory into the memory subsystem in response to said stream hit detector detecting a load instruction data address that hits in the data stream, wherein said stream prefetch engine selects a cache memory level in the hierarchy for prefetching the cache line of the data stream into based on the memory subsystem configuration and on said relative urgency with which said data stream is needed specified by said locality characteristic. 13. The computer program product as recited in claim 12, wherein a first predetermined value of said parameter specifies said data stream is relatively urgently needed and wherein said stream prefetch engine is configured to attempt to prefetch said cache line into a low level of the cache memory hierarchy relative to the memory subsystem configuration, wherein a second predetermined value of said parameter specifies said data stream is relatively non-urgently needed, and wherein said stream prefetch engine is configured to attempt to prefetch said cache line into a high level of the cache memory hierarchy relative to the memory subsystem configuration. 14. The computer program product as recited in claim 12, wherein a third predetermined value of said parameter specifies whether said data stream is relatively, moderately or urgently needed, and wherein said stream prefetch engine is configured to attempt to prefetch said cache line into a middle level of the cache memory hierarchy relative to the memory subsystem configuration. 15. A data stream prefetching microprocessor coupled to a system memory, comprising: a memory subsystem, comprising at least one cache memory, said cache memory configured to evict cache lines from said at least one cache memory based on a cache line replacement policy; an instruction decoder, configured to decode an instruction, said instruction specifying a data stream and a parameter specifying a locality characteristic of said data stream, wherein the locality characteristic specifies a relative ephemerality of the data stream; and a stream prefetch unit, coupled to said instruction decoder and said memory subsystem, comprising: a stream hit detector, coupled to said instruction decoder, configured to detect load instruction data addresses that are within the data stream; and a stream prefetch engine, coupled to said stream hit detector, configured to prefetch a cache line of the data stream from the system memory into the memory subsystem in response to said stream hit detector detecting a load instruction data address that is within the data stream, wherein said stream prefetch engine instructs said memory subsystem to mark said prefetched cache line for early eviction according to a cache line replacement policy as specified by the relative ephemerality of the data stream. 16. The microprocessor as recited in claim 15, wherein said stream prefetch engine instructs said memory subsystem to mark said prefetched cache line for late eviction if said parameter specifies a second predetermined value. 17. The microprocessor as recited in claim 16, wherein said memory subsystem is configured to set said cache line as most-recently-used in response to said stream prefetch engine instructing said memory subsystem to mark said prefetched cache line for late eviction. 18. The microprocessor as recited in claim 15, wherein said stream prefetch engine instructs said memory subsystem to mark said prefetched cache line for normal eviction if said parameter specifies a third predetermined value. 19. The microprocessor as recited in claim 15, wherein said memory subsystem is configured to set said cache line as least-recently-used in response to said stream prefetch engine instructing said memory subsystem to mark said prefetched cache line for early eviction. 20. A computer program product for use with a computing device, the computer program product comprising: a computer readable storage medium, having computer readable program code embodied thereon for providing a data stream prefetching microprocessor coupled to a system memory, said computer readable program code comprising: first computer readable program code for providing a memory subsystem, comprising at least one cache memory, said cache memory configured to evict cache lines from said at least one cache memory based on a cache line replacement policy; second computer readable program code for providing an instruction decoder, configured to decode an instruction, said instruction specifying a data stream and a parameter specifying a locality characteristic of said data stream, wherein the locality characteristic specifies a relative ephemerality of the data stream; and third computer readable program code for providing a stream prefetch unit, coupled to said instruction decoder and said memory subsystem, comprising: a stream hit detector, coupled to said instruction decoder, configured to detect load instruction data addresses that are within the data stream; and a stream prefetch engine, coupled to said stream hit detector, configured to prefetch a cache line of the data stream from the system memory into the memory subsystem in response to said stream hit detector detecting a load instruction data address that is within the data stream, wherein said stream prefetch engine instructs said memory subsystem to mark said prefetched cache line for early eviction according to said cache line replacement policy, as determined by the relative ephemerality of the data stream. 21. The computer program product as recited in claim 20, wherein said stream prefetch engine instructs said memory subsystem to mark said prefetched cache line as having a cache line replacement strategy of late eviction if said parameter specifies a second predetermined value. 22. The computer program product as recited in claim 21, wherein said memory subsystem is configured to set said cache line as most-recently-used in response to said stream prefetch engine instructing said memory subsystem to mark said prefetched cache line as having a cache line replacement strategy of late eviction. 23. The computer program product as recited in claim 20, wherein said stream prefetch engine instructs said memory subsystem to mark said prefetched cache line as having a cache line replacement strategy of normal eviction if said parameter specifies a third predetermined value. 24. The computer program product as recited in claim 20, wherein said memory subsystem is configured to set said cache line as least-recently-used in response to said stream prefetch engine instructing said memory subsystem to mark said prefetched cache line as having a cache line replacement strategy of early eviction.
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