IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
UP-0391000
(2006-03-27)
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등록번호 |
US-7669097
(2010-04-09)
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발명자
/ 주소 |
- Teig, Steven
- Redgrave, Jason
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출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
25 인용 특허 :
168 |
초록
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A configurable integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data, an error detection circuitry for detecting an error and a circuit that outputs from the IC an uncorrectable error signal indica
A configurable integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data, an error detection circuitry for detecting an error and a circuit that outputs from the IC an uncorrectable error signal indicating the detection of an error. The configurable IC has a circuit inside of the IC that causes the IC to reset when the error circuitry detects an uncorrectable error. In another embodiment, the circuit that causes the IC to reset is located outside of the IC.
대표청구항
▼
What is claimed is: 1. An integrated circuit (“IC”) comprising: a) a configuration memory for storing configuration data; b) error detection circuitry for (i) receiving configuration data from the configuration memory, (ii) detecting and correcting errors in the configuration data tha
What is claimed is: 1. An integrated circuit (“IC”) comprising: a) a configuration memory for storing configuration data; b) error detection circuitry for (i) receiving configuration data from the configuration memory, (ii) detecting and correcting errors in the configuration data that fall within a first class of errors, and (iii) detecting errors in the configuration data that fall within a second class of errors and generating an uncorrectable error signal after detecting a second class error in order to indicate an uncorrectable error; and c) a configurable circuit for receiving the configuration data from the error detection circuitry. 2. The IC of claim 1 further comprising a circuit for resetting the IC when the error detection circuitry detects an uncorrectable error. 3. The IC of claim 1, wherein a circuit inside of the IC receives the uncorrectable error signal and, in response, loads new configuration data into the configurable IC, wherein the source of the new configuration data is from a source outside of the configurable IC. 4. The IC of claim 1, wherein a circuit inside of the IC receives the uncorrectable error signal and, in response, loads new configuration data into the configurable IC, wherein the source of the new configuration data is from a source inside of the configurable IC. 5. The IC of claim 1, wherein a circuit outside of the IC causes the IC to reset when the error circuitry detects an uncorrectable error. 6. The IC of claim 1, wherein a circuit outside of the IC receives the uncorrectable error signal and, in response, loads new configuration data into the configurable IC, wherein the source of the new configuration data is from a source outside of the configurable IC. 7. The IC of claim 1, wherein a circuit outside of the IC receives the uncorrectable error signal and, in response, loads new configuration data into the configurable IC, wherein the source of the new configuration data is from a source inside of the configurable IC. 8. The IC of claim 1, wherein the first class of errors includes errors of n bits, wherein n≧1. 9. The IC of claim 8, wherein the second class of errors includes errors of m bits, wherein m>n. 10. An electronic device comprising an integrated circuit (“IC”), said IC comprising: a) a configuration memory for storing configuration data; b) a configurable circuit for receiving the configuration data; and c) a configuration retrieval circuit for supplying the configuration data from the configuration memory to the configurable circuit, the configuration retrieval circuit comprising an error detection circuit for detecting whether the configuration data has an error before the configuration retrieval circuit supplies the configuration data to the configurable circuit. 11. The electronic device of claim 10, wherein the error correction circuit is further for outputting an uncorrectable error signal when the detected error is an uncorrectable error. 12. The electronic device of claim 11, wherein a circuit inside of the IC receives the uncorrectable error signal and, in response, loads new configuration data into the configurable IC, wherein the source of the new configuration data is from a source inside of the IC. 13. The electronic device of claim 11, wherein a circuit outside of the IC receives the uncorrectable error signal and, in response, loads new configuration data into the configurable IC, wherein the source of the new configuration data is from a source outside of the IC. 14. The electronic device of claim 10, wherein the error detection circuit is also an error correction circuit for correcting errors in the configuration data that fall within a first class of errors. 15. The electronic device of claim 14, wherein the first class of errors includes errors of n bits, wherein n≧1. 16. The electronic device of claim 15, wherein the error detection circuit is for detecting errors in the configuration data that fall within a second class of errors. 17. The electronic device of claim 16, wherein the second class of errors includes errors of m bits, wherein m>n. 18. An integrated circuit (“IC”) comprising: a) a plurality of configuration storage elements for storing a plurality of configuration data sets; b) a reconfigurable circuit for receiving different configuration data sets in different clock cycles; and c) a multi-tier data transfer structure for transferring different configuration data sets to the reconfigurable circuit during different clock cycles, said multi-tier data transfer structure comprising at least one error detection circuit for determining whether a configuration data set includes an error. 19. The IC of claim 18, wherein the multi-tier data transfer structure further comprises a first set of selection circuits and a second set of selection circuits; wherein during a particular clock cycle, the first set of selection circuits supplies a configuration data set to the reconfigurable circuit for a particular clock cycle, while the second set of selection circuits pre-fetches a configuration data set to supply to the reconfigurable circuit during a clock cycle subsequent to the particular clock cycle. 20. The IC of claim 19, wherein the multi-tier data transfer structure further comprises a plurality of error detection circuits between the first set of selection circuits and the second set of selection circuits; wherein the plurality of error detection circuits are for determining whether the pre-fetched configuration data sets provided by the second set of selection circuits have errors before supplying the pre-fetched configuration data sets to the first set of selection circuits. 21. The IC of claim 19 wherein the error detection circuit is positioned after the first set of selection circuits to check whether the configuration data set output by the first set of selection circuits includes an error before supplying the configuration data set output by the first set of selection circuits to the reconfigurable circuit. 22. The IC of claim 21 wherein the multi-tier data transfer structure further comprises a retiming circuit after the error detection circuit for receiving the configuration data set from the error detection circuit and retiming the configuration data set to make the configuration data set synchronous with the operation of the reconfigurable circuit before providing the configuration data set to the reconfigurable circuit.
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